dm642_syn.fit.smsg

一个用vHDL语言编的同步程序

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Thu Apr 09 20:17:57 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off DM642_syn -c DM642_syn
Info: Selected device EP1C6Q240C8 for design "DM642_syn"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 65 of 65 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP1C12Q240C8 is compatible
Info: Fitter converted 2 user pins into dedicated programming pins
    Info: Pin ~nCSO~ is reserved at location 24
    Info: Pin ~ASDO~ is reserved at location 37
Warning: No exact pin location assignment(s) for 3 pins of 3 total pins
    Info: Pin syn_ir not assigned to an exact location on the device
    Info: Pin syn_dm642 not assigned to an exact location on the device
    Info: Pin clk not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources
Info: Automatically promoted signal "clk" to use Global clock in PIN 29
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing: elapsed time is 00:00:00
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 2 (unused VREF, 3.30 VCCIO, 0 input, 2 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  41 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  48 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  45 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  48 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 4.624 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X12_Y16; Fanout = 6; REG Node = 'syn_count[6]'
    Info: 2: + IC(1.350 ns) + CELL(0.114 ns) = 1.464 ns; Loc. = LAB_X11_Y17; Fanout = 1; COMB Node = 'LessThan1~277'
    Info: 3: + IC(1.367 ns) + CELL(0.292 ns) = 3.123 ns; Loc. = LAB_X13_Y16; Fanout = 1; COMB Node = 'process0~238'
    Info: 4: + IC(0.539 ns) + CELL(0.114 ns) = 3.776 ns; Loc. = LAB_X13_Y16; Fanout = 1; COMB Node = 'process0~239'
    Info: 5: + IC(0.539 ns) + CELL(0.309 ns) = 4.624 ns; Loc. = LAB_X13_Y16; Fanout = 1; REG Node = 'syn_dm642~reg0'
    Info: Total cell delay = 0.829 ns ( 17.93 % )
    Info: Total interconnect delay = 3.795 ns ( 82.07 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%
    Info: The peak interconnect region extends from location X0_Y11 to location X11_Y21
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
    Info: Allocated 204 megabytes of memory during processing
    Info: Processing ended: Thu Apr 09 20:18:14 2009
    Info: Elapsed time: 00:00:17