hanxu.map.rpt
来自「机器状态机。控制工作方式。用vhdl写的。很不错哦」· RPT 代码 · 共 696 行 · 第 1/4 页
RPT
696 行
; PORT_CLK1 ; PORT_UNUSED ; Untyped ;
; PORT_CLK2 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLK3 ; PORT_UNUSED ; Untyped ;
; PORT_CLK4 ; PORT_UNUSED ; Untyped ;
; PORT_CLK5 ; PORT_UNUSED ; Untyped ;
; PORT_SCANDATA ; PORT_UNUSED ; Untyped ;
; PORT_SCANDATAOUT ; PORT_UNUSED ; Untyped ;
; PORT_SCANDONE ; PORT_UNUSED ; Untyped ;
; PORT_SCLKOUT1 ; PORT_UNUSED ; Untyped ;
; PORT_SCLKOUT0 ; PORT_UNUSED ; Untyped ;
; PORT_ACTIVECLOCK ; PORT_UNUSED ; Untyped ;
; PORT_CLKLOSS ; PORT_UNUSED ; Untyped ;
; PORT_INCLK1 ; PORT_UNUSED ; Untyped ;
; PORT_INCLK0 ; PORT_USED ; Untyped ;
; PORT_FBIN ; PORT_UNUSED ; Untyped ;
; PORT_PLLENA ; PORT_UNUSED ; Untyped ;
; PORT_CLKSWITCH ; PORT_UNUSED ; Untyped ;
; PORT_ARESET ; PORT_UNUSED ; Untyped ;
; PORT_PFDENA ; PORT_UNUSED ; Untyped ;
; PORT_SCANCLK ; PORT_UNUSED ; Untyped ;
; PORT_SCANACLR ; PORT_UNUSED ; Untyped ;
; PORT_SCANREAD ; PORT_UNUSED ; Untyped ;
; PORT_SCANWRITE ; PORT_UNUSED ; Untyped ;
; PORT_ENABLE0 ; PORT_UNUSED ; Untyped ;
; PORT_ENABLE1 ; PORT_UNUSED ; Untyped ;
; PORT_LOCKED ; PORT_UNUSED ; Untyped ;
; M_TEST_SOURCE ; 5 ; Untyped ;
; C0_TEST_SOURCE ; 5 ; Untyped ;
; C1_TEST_SOURCE ; 5 ; Untyped ;
; C2_TEST_SOURCE ; 5 ; Untyped ;
; C3_TEST_SOURCE ; 5 ; Untyped ;
; C4_TEST_SOURCE ; 5 ; Untyped ;
; C5_TEST_SOURCE ; 5 ; Untyped ;
; DEVICE_FAMILY ; Cyclone II ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+-------------------------------+-------------------+----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+----------------------------------------------------------+
; Parameter Settings for User Entity Instance: 74161:inst7 ;
+------------------------+------------+--------------------+
; Parameter Name ; Value ; Type ;
+------------------------+------------+--------------------+
; DEVICE_FAMILY ; Cyclone II ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+------------+--------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+----------------------------------------------------------+
; Parameter Settings for User Entity Instance: 74161:inst6 ;
+------------------------+------------+--------------------+
; Parameter Name ; Value ; Type ;
+------------------------+------------+--------------------+
; DEVICE_FAMILY ; Cyclone II ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+------------+--------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Mon Oct 06 21:10:51 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off hanxu -c hanxu
Info: Found 2 design units, including 1 entities, in source file image_convert.vhd
Info: Found design unit 1: image_convert-Behavioral
Info: Found entity 1: image_convert
Info: Found 2 design units, including 1 entities, in source file fenpin.vhd
Info: Found design unit 1: fenpin-behav
Info: Found entity 1: fenpin
Warning (10463): Verilog HDL Declaration warning at QJSTDOUT2.v(6): "int" is SystemVerilog-2005 keyword
Warning (10463): Verilog HDL Declaration warning at QJSTDOUT2.v(14): "int" is SystemVerilog-2005 keyword
Warning (10463): Verilog HDL Declaration warning at QJSTDOUT2.v(22): "int" is SystemVerilog-2005 keyword
Warning (10463): Verilog HDL Declaration warning at QJSTDOUT2.v(63): "int" is SystemVerilog-2005 keyword
Warning (10463): Verilog HDL Declaration warning at QJSTDOUT2.v(64): "int" is SystemVerilog-2005 keyword
Info: Found 1 design units, including 1 entities, in source file QJSTDOUT2.v
Info: Found entity 1: QJSTDOUT2
Warning (10463): Verilog HDL Declaration warning at QJSTDOUT_original.v(6): "int" is SystemVerilog-2005 keyword
Warning (10463): Verilog HDL Declaration warning at QJSTDOUT_original.v(14): "int" is SystemVerilog-2005 keyword
Warning (10463): Verilog HDL Declaration warning at QJSTDOUT_original.v(22): "int" is SystemVerilog-2005 keyword
Warning (10463): Verilog HDL Declaration warning at QJSTDOUT_original.v(58): "int" is SystemVerilog-2005 keyword
Warning (10463): Verilog HDL Declaration warning at QJSTDOUT_original.v(59): "int" is SystemVerilog-2005 keyword
Info: Found 1 design units, including 1 entities, in source file QJSTDOUT_original.v
Info: Found entity 1: QJSTDOUT_original
Info: Found 1 design units, including 1 entities, in source file block.bdf
Info: Found entity 1: block
Info: Found 2 design units, including 1 entities, in source file driver.vhd
Info: Found design unit 1: driver-bh
Info: Found entity 1: driver
Info: Found 2 design units, including 1 entities, in source file control.vhd
Info: Found design unit 1: control-behav
Info: Found entity 1: control
Info: Found 2 design units, including 1 entities, in source file fuwei.vhd
Info: Found design unit 1: fuwei-a
Info: Found entity 1: fuwei
Info: Elaborating entity "block" for the top level hierarchy
Warning: Port "int" of type image_convert and instance "inst" is missing source signal
Warning: Pin "OTR" not connected
Info: Elaborating entity "image_convert" for hierarchy "image_convert:inst"
Warning (10492): VHDL Process Statement warning at image_convert.vhd(119): signal "reset" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at image_convert.vhd(133): signal "reset" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10034): Output port "video_clk" at image_convert.vhd(11) has no driver
Info: Elaborating entity "fenpin" for hierarchy "fenpin:inst1"
Warning: Using design file pll.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: pll
Info: Elaborating entity "pll" for hierarchy "pll:inst4"
Info: Found 1 design units, including 1 entities, in source file ../../altera_q60/quartus60/libraries/megafunctions/altpll.tdf
Info: Found entity 1: altpll
Info: Elaborating entity "altpll" for hierarchy "pll:inst4|altpll:altpll_component"
Info: Elaborated megafunction instantiation "pll:inst4|altpll:altpll_component"
Info: Elaborating entity "fuwei" for hierarchy "fuwei:inst9"
Info: Elaborating entity "control" for hierarchy "control:inst3"
Info: Elaborating entity "driver" for hierarchy "driver:inst5"
Info: Found 1 design units, including 1 entities, in source file ../../altera_q60/quartus60/libraries/others/maxplus2/74161.tdf
Info: Found entity 1: 74161
Info: Elaborating entity "74161" for hierarchy "74161:inst7"
Info: Elaborated megafunction instantiation "74161:inst7"
Info: Found 1 design units, including 1 entities, in source file ../../altera_q60/quartus60/libraries/others/maxplus2/f74161.bdf
Info: Found entity 1: f74161
Info: Elaborating entity "f74161" for hierarchy "74161:inst7|f74161:sub"
Info: Elaborated megafunction instantiation "74161:inst7|f74161:sub", which is child of megafunction instantiation "74161:inst7"
Info: Elaborating entity "74161" for hierarchy "74161:inst6"
Info: Elaborated megafunction instantiation "74161:inst6"
Warning: Reduced register "driver:inst5|din[0]" with stuck data_in port to stuck value GND
Info: Ignored 3 buffer(s)
Info: Ignored 3 CARRY buffer(s)
Info: Duplicate registers merged to single register
Info: Duplicate register "driver:inst5|sclk" merged to single register "driver:inst5|sclk0"
Info: Duplicate register "fenpin:inst2|clk_num" merged to single register "fenpin:inst2|clkout", power-up level changed
Info: Duplicate register "fenpin:inst10|clk_num" merged to single register "fenpin:inst2|clkout"
Info: Duplicate register "fenpin:inst10|clkout" merged to single register "fenpin:inst2|clkout", power-up level changed
Info: Duplicate register "fenpin:inst1|clk_num" merged to single register "fenpin:inst1|clkout", power-up level changed
Info: Duplicate register "image_convert:inst|read_write_toggle" merged to single register "fenpin:inst2|clkout"
Warning: Reduced register "driver:inst5|din[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "driver:inst5|din[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "driver:inst5|din[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "driver:inst5|din[4]" with stuck data_in port to stuck value GND
Warning: Reduced register "driver:inst5|din[5]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
Info: Duplicate register "driver:inst5|countclkstop[0]" merged to single register "driver:inst5|countclk0[0]"
Info: Duplicate registers merged to single register
Info: Duplicate register "driver:inst5|countclk0[1]" merged to single register "driver:inst5|sclk0", power-up level changed
Warning: Output pins are stuck at VCC or GND
Warning: Pin "reset_DSP" stuck at VCC
Warning: Pin "data[15]" stuck at GND
Warning: Pin "data[14]" stuck at GND
Warning: Design contains 1 input pin(s) that do not drive logic
Warning: No output dependent on input pin "OTR"
Info: Implemented 461 device resources after synthesis - the final resource count might be different
Info: Implemented 18 input pins
Info: Implemented 50 output pins
Info: Implemented 14 bidirectional pins
Info: Implemented 378 logic cells
Info: Implemented 1 ClockLock PLLs
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 28 warnings
Info: Processing ended: Mon Oct 06 21:11:12 2008
Info: Elapsed time: 00:00:21
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?