fenpin.vhd

来自「机器状态机。控制工作方式。用vhdl写的。很不错哦」· VHDL 代码 · 共 23 行

--PLL输出的时钟分频为处理时钟
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fenpin is
   port (
           clk:in std_logic;
         clkout:out std_logic);
end fenpin;
architecture behav of fenpin is
signal clk_num:std_logic:='0';
begin
  process(clk)
     begin
       if(clk'event and clk='1')then
          -- if(clk_num='0') then
              
           clk_num<=not clk_num;
           clkout<=clk_num;
       end if;
  end process;
end behav;