hanxu.sim.rpt

机器状态机。控制工作方式。用vhdl写的。很不错哦

; Trigger vector comparison with the specified mode                                          ; INPUT_EDGE                                ; INPUT_EDGE    ;
; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off                                       ; Off           ;
; Overwrite Waveform Inputs With Simulation Outputs                                          ; On                                        ;               ;
; Glitch Filtering                                                                           ; Off                                       ; Off           ;
+--------------------------------------------------------------------------------------------+-------------------------------------------+---------------+


+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+--------------------------------------------------------------------+
; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;      40.79 % ;
; Total nodes checked                                 ; 2212         ;
; Total output ports checked                          ; 2324         ;
; Total output ports with complete 1/0-value coverage ; 948          ;
; Total output ports with no 1/0-value coverage       ; 1256         ;
; Total output ports with no 1-value coverage         ; 1263         ;
; Total output ports with no 0-value coverage         ; 1369         ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                                                                           ;
+-----------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                     ; Output Port Name                                                                                   ; Output Port Type ;
+-----------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------+------------------+
; |block|clk                                                                                    ; |block|clk                                                                                         ; out              ;
; |block|CE                                                                                     ; |block|CE                                                                                          ; pin_out          ;
; |block|OE                                                                                     ; |block|OE                                                                                          ; pin_out          ;
; |block|mc                                                                                     ; |block|mc                                                                                          ; pin_out          ;
; |block|ad_clk                                                                                 ; |block|ad_clk                                                                                      ; pin_out          ;
; |block|clk_bai                                                                                ; |block|clk_bai                                                                                     ; pin_out          ;
; |block|sclk                                                                                   ; |block|sclk                                                                                        ; pin_out          ;
; |block|adr1061[11]                                                                            ; |block|adr1061[11]                                                                                 ; pin_out          ;
; |block|adr1061[10]                                                                            ; |block|adr1061[10]                                                                                 ; pin_out          ;
; |block|adr1061[9]                                                                             ; |block|adr1061[9]                                                                                  ; pin_out          ;
; |block|adr1061[8]                                                                             ; |block|adr1061[8]                                                                                  ; pin_out          ;
; |block|adr1061[7]                                                                             ; |block|adr1061[7]                                                                                  ; pin_out          ;
; |block|adr1061[6]                                                                             ; |block|adr1061[6]                                                                                  ; pin_out          ;
; |block|adr1061[5]                                                                             ; |block|adr1061[5]                                                                                  ; pin_out          ;
; |block|adr1061[4]                                                                             ; |block|adr1061[4]                                                                                  ; pin_out          ;
; |block|adr1061[3]                                                                             ; |block|adr1061[3]                                                                                  ; pin_out          ;
; |block|adr1061[2]                                                                             ; |block|adr1061[2]                                                                                  ; pin_out          ;
; |block|adr1061[1]                                                                             ; |block|adr1061[1]                                                                                  ; pin_out          ;
; |block|adr1061[0]                                                                             ; |block|adr1061[0]                                                                                  ; pin_out          ;
; |block|74161:inst6|f74161:sub|110                                                             ; |block|74161:inst6|f74161:sub|110                                                                  ; out              ;
; |block|74161:inst6|f74161:sub|107                                                             ; |block|74161:inst6|f74161:sub|107                                                                  ; out0             ;
; |block|74161:inst6|f74161:sub|94                                                              ; |block|74161:inst6|f74161:sub|94                                                                   ; out0             ;
; |block|74161:inst6|f74161:sub|99                                                              ; |block|74161:inst6|f74161:sub|99                                                                   ; out              ;
; |block|74161:inst6|f74161:sub|97                                                              ; |block|74161:inst6|f74161:sub|97                                                                   ; out0             ;
; |block|74161:inst6|f74161:sub|84                                                              ; |block|74161:inst6|f74161:sub|84                                                                   ; out0             ;
; |block|74161:inst6|f74161:sub|87                                                              ; |block|74161:inst6|f74161:sub|87                                                                   ; out              ;
; |block|74161:inst6|f74161:sub|90                                                              ; |block|74161:inst6|f74161:sub|90                                                                   ; out0             ;
; |block|74161:inst6|f74161:sub|81                                                              ; |block|74161:inst6|f74161:sub|81                                                                   ; out0             ;
; |block|74161:inst6|f74161:sub|9                                                               ; |block|74161:inst6|f74161:sub|9                                                                    ; out              ;
; |block|driver:inst5|sclk~0                                                                    ; |block|driver:inst5|sclk~0                                                                         ; out              ;
; |block|driver:inst5|countclk0~0                                                               ; |block|driver:inst5|countclk0~0                                                                    ; out              ;
; |block|driver:inst5|countclk0~1                                                               ; |block|driver:inst5|countclk0~1                                                                    ; out              ;
; |block|driver:inst5|countclk0~2                                                               ; |block|driver:inst5|countclk0~2                                                                    ; out              ;
; |block|driver:inst5|countclk0~3                                                               ; |block|driver:inst5|countclk0~3                                                                    ; out              ;
; |block|driver:inst5|countsclk0~1                                                              ; |block|driver:inst5|countsclk0~1                                                                   ; out              ;
; |block|driver:inst5|countsclk0~2                                                              ; |block|driver:inst5|countsclk0~2                                                                   ; out              ;
; |block|driver:inst5|countsclk0~3                                                              ; |block|driver:inst5|countsclk0~3                                                                   ; out              ;
; |block|driver:inst5|countsclk0~4                                                              ; |block|driver:inst5|countsclk0~4                                                                   ; out              ;
; |block|driver:inst5|countsclk0~5                                                              ; |block|driver:inst5|countsclk0~5                                                                   ; out              ;
; |block|driver:inst5|countsclk0~6                                                              ; |block|driver:inst5|countsclk0~6                                                                   ; out              ;