hanxu.tan.rpt

机器状态机。控制工作方式。用vhdl写的。很不错哦

; Worst-case th                                          ; N/A       ; None                             ; -0.575 ns                        ; datavlid                                ; image_convert:inst|sram_we~reg0         ; --                                      ; clk                                     ; 0            ;
; Clock Setup: 'pll:inst4|altpll:altpll_component|_clk0' ; 13.119 ns ; 25.00 MHz ( period = 40.000 ns ) ; 72.66 MHz ( period = 13.762 ns ) ; image_convert:inst|ram_toggle           ; image_convert:inst|sram_addr[19]        ; pll:inst4|altpll:altpll_component|_clk0 ; pll:inst4|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'clk'                                     ; 14.449 ns ; 50.00 MHz ( period = 20.000 ns ) ; 180.15 MHz ( period = 5.551 ns ) ; driver:inst5|countsclk0[1]              ; driver:inst5|din[7]                     ; clk                                     ; clk                                     ; 0            ;
; Clock Setup: 'datavlid'                                ; N/A       ; None                             ; 337.15 MHz ( period = 2.966 ns ) ; image_convert:inst|line_count[1]        ; image_convert:inst|line_count[9]        ; datavlid                                ; datavlid                                ; 0            ;
; Clock Hold: 'pll:inst4|altpll:altpll_component|_clk0'  ; 0.499 ns  ; 25.00 MHz ( period = 40.000 ns ) ; N/A                              ; image_convert:inst|write_pixel_count[0] ; image_convert:inst|write_pixel_count[0] ; pll:inst4|altpll:altpll_component|_clk0 ; pll:inst4|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'clk'                                      ; 0.499 ns  ; 50.00 MHz ( period = 20.000 ns ) ; N/A                              ; driver:inst5|countfs[10]                ; driver:inst5|countfs[10]                ; clk                                     ; clk                                     ; 0            ;
; Total number of failed paths                           ;           ;                                  ;                                  ;                                         ;                                         ;                                         ;                                         ; 0            ;
+--------------------------------------------------------+-----------+----------------------------------+----------------------------------+-----------------------------------------+-----------------------------------------+-----------------------------------------+-----------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C20F484C8       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                          ;
+-----------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                         ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+-----------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; pll:inst4|altpll:altpll_component|_clk0 ;                    ; PLL output ; 25.0 MHz         ; 0.000 ns      ; 0.000 ns     ; clk      ; 1                     ; 2                   ; -2.616 ns ;              ;
; clk                                     ;                    ; User Pin   ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; datavlid                                ;                    ; User Pin   ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; lignel1                                 ;                    ; User Pin   ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
+-----------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'pll:inst4|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                             ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------+----------------------------------+-----------------------------------------+-----------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                    ; To                               ; From Clock                              ; To Clock                                ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;