11114.tan.rpt

秒表功能的显示 LCD1602显示,自动加1 VHDL

+-------+--------------+------------+------+--------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To     ; To Clock ;
+-------+--------------+------------+------+--------+----------+
; N/A   ; None         ; 4.006 ns   ; EN   ; CQI[0] ; CLK      ;
; N/A   ; None         ; 4.006 ns   ; EN   ; CQI[2] ; CLK      ;
; N/A   ; None         ; 4.006 ns   ; EN   ; CQI[3] ; CLK      ;
; N/A   ; None         ; 4.006 ns   ; EN   ; CQI[1] ; CLK      ;
+-------+--------------+------------+------+--------+----------+


+-----------------------------------------------------------------+
; tco                                                             ;
+-------+--------------+------------+--------+-------+------------+
; Slack ; Required tco ; Actual tco ; From   ; To    ; From Clock ;
+-------+--------------+------------+--------+-------+------------+
; N/A   ; None         ; 8.792 ns   ; CQI[0] ; COUT  ; CLK        ;
; N/A   ; None         ; 8.784 ns   ; CQI[1] ; COUT  ; CLK        ;
; N/A   ; None         ; 8.664 ns   ; CQI[2] ; COUT  ; CLK        ;
; N/A   ; None         ; 8.586 ns   ; CQI[3] ; COUT  ; CLK        ;
; N/A   ; None         ; 7.174 ns   ; CQI[0] ; CQ[0] ; CLK        ;
; N/A   ; None         ; 6.775 ns   ; CQI[1] ; CQ[1] ; CLK        ;
; N/A   ; None         ; 6.453 ns   ; CQI[2] ; CQ[2] ; CLK        ;
; N/A   ; None         ; 6.446 ns   ; CQI[3] ; CQ[3] ; CLK        ;
+-------+--------------+------------+--------+-------+------------+


+--------------------------------------------------------------------+
; th                                                                 ;
+---------------+-------------+-----------+------+--------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To     ; To Clock ;
+---------------+-------------+-----------+------+--------+----------+
; N/A           ; None        ; -3.954 ns ; EN   ; CQI[0] ; CLK      ;
; N/A           ; None        ; -3.954 ns ; EN   ; CQI[2] ; CLK      ;
; N/A           ; None        ; -3.954 ns ; EN   ; CQI[3] ; CLK      ;
; N/A           ; None        ; -3.954 ns ; EN   ; CQI[1] ; CLK      ;
+---------------+-------------+-----------+------+--------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Mon May 25 00:39:25 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off 11114 -c 11114 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" Internal fmax is restricted to 275.03 MHz between source register "CQI[1]" and destination register "CQI[0]"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.338 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y14_N7; Fanout = 6; REG Node = 'CQI[1]'
            Info: 2: + IC(0.600 ns) + CELL(0.738 ns) = 1.338 ns; Loc. = LC_X1_Y14_N9; Fanout = 6; REG Node = 'CQI[0]'
            Info: Total cell delay = 0.738 ns ( 55.16 % )
            Info: Total interconnect delay = 0.600 ns ( 44.84 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "CLK" to destination register is 2.954 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 4; CLK Node = 'CLK'
                Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y14_N9; Fanout = 6; REG Node = 'CQI[0]'
                Info: Total cell delay = 2.180 ns ( 73.80 % )
                Info: Total interconnect delay = 0.774 ns ( 26.20 % )
            Info: - Longest clock path from clock "CLK" to source register is 2.954 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 4; CLK Node = 'CLK'
                Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y14_N7; Fanout = 6; REG Node = 'CQI[1]'
                Info: Total cell delay = 2.180 ns ( 73.80 % )
                Info: Total interconnect delay = 0.774 ns ( 26.20 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "CQI[0]" (data pin = "EN", clock pin = "CLK") is 4.006 ns
    Info: + Longest pin to register delay is 6.923 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_21; Fanout = 4; PIN Node = 'EN'
        Info: 2: + IC(4.587 ns) + CELL(0.867 ns) = 6.923 ns; Loc. = LC_X1_Y14_N9; Fanout = 6; REG Node = 'CQI[0]'
        Info: Total cell delay = 2.336 ns ( 33.74 % )
        Info: Total interconnect delay = 4.587 ns ( 66.26 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 2.954 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 4; CLK Node = 'CLK'
        Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y14_N9; Fanout = 6; REG Node = 'CQI[0]'
        Info: Total cell delay = 2.180 ns ( 73.80 % )
        Info: Total interconnect delay = 0.774 ns ( 26.20 % )
Info: tco from clock "CLK" to destination pin "COUT" through register "CQI[0]" is 8.792 ns
    Info: + Longest clock path from clock "CLK" to source register is 2.954 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 4; CLK Node = 'CLK'
        Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y14_N9; Fanout = 6; REG Node = 'CQI[0]'
        Info: Total cell delay = 2.180 ns ( 73.80 % )
        Info: Total interconnect delay = 0.774 ns ( 26.20 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 5.614 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y14_N9; Fanout = 6; REG Node = 'CQI[0]'
        Info: 2: + IC(1.085 ns) + CELL(0.114 ns) = 1.199 ns; Loc. = LC_X1_Y14_N4; Fanout = 1; COMB Node = 'Equal0~31'
        Info: 3: + IC(2.307 ns) + CELL(2.108 ns) = 5.614 ns; Loc. = PIN_63; Fanout = 0; PIN Node = 'COUT'
        Info: Total cell delay = 2.222 ns ( 39.58 % )
        Info: Total interconnect delay = 3.392 ns ( 60.42 % )
Info: th for register "CQI[0]" (data pin = "EN", clock pin = "CLK") is -3.954 ns
    Info: + Longest clock path from clock "CLK" to destination register is 2.954 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 4; CLK Node = 'CLK'
        Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y14_N9; Fanout = 6; REG Node = 'CQI[0]'
        Info: Total cell delay = 2.180 ns ( 73.80 % )
        Info: Total interconnect delay = 0.774 ns ( 26.20 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 6.923 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_21; Fanout = 4; PIN Node = 'EN'
        Info: 2: + IC(4.587 ns) + CELL(0.867 ns) = 6.923 ns; Loc. = LC_X1_Y14_N9; Fanout = 6; REG Node = 'CQI[0]'
        Info: Total cell delay = 2.336 ns ( 33.74 % )
        Info: Total interconnect delay = 4.587 ns ( 66.26 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Mon May 25 00:39:25 2009
    Info: Elapsed time: 00:00:01