11114.tan.rpt

秒表功能的显示 LCD1602显示,自动加1 VHDL

Timing Analyzer report for 11114
Mon May 25 00:39:25 2009
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'CLK'
  6. tsu
  7. tco
  8. th
  9. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                        ;
+------------------------------+-------+---------------+------------------------------------------------+--------+--------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                                    ; From   ; To     ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+--------+--------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 4.006 ns                                       ; EN     ; CQI[1] ; --         ; CLK      ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 8.792 ns                                       ; CQI[0] ; COUT   ; CLK        ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; -3.954 ns                                      ; EN     ; CQI[1] ; --         ; CLK      ; 0            ;
; Clock Setup: 'CLK'           ; N/A   ; None          ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CQI[1] ; CQI[0] ; CLK        ; CLK      ; 0            ;
; Total number of failed paths ;       ;               ;                                                ;        ;        ;            ;          ; 0            ;
+------------------------------+-------+---------------+------------------------------------------------+--------+--------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                                   ;
+-------+------------------------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From   ; To     ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CQI[1] ; CQI[0] ; CLK        ; CLK      ; None                        ; None                      ; 1.338 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CQI[1] ; CQI[3] ; CLK        ; CLK      ; None                        ; None                      ; 1.337 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CQI[1] ; CQI[2] ; CLK        ; CLK      ; None                        ; None                      ; 1.336 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CQI[1] ; CQI[1] ; CLK        ; CLK      ; None                        ; None                      ; 1.335 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CQI[3] ; CQI[3] ; CLK        ; CLK      ; None                        ; None                      ; 1.159 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CQI[3] ; CQI[0] ; CLK        ; CLK      ; None                        ; None                      ; 1.158 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CQI[3] ; CQI[2] ; CLK        ; CLK      ; None                        ; None                      ; 1.158 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CQI[3] ; CQI[1] ; CLK        ; CLK      ; None                        ; None                      ; 1.157 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CQI[0] ; CQI[2] ; CLK        ; CLK      ; None                        ; None                      ; 1.082 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CQI[0] ; CQI[1] ; CLK        ; CLK      ; None                        ; None                      ; 1.081 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CQI[0] ; CQI[3] ; CLK        ; CLK      ; None                        ; None                      ; 1.079 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CQI[0] ; CQI[0] ; CLK        ; CLK      ; None                        ; None                      ; 1.077 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CQI[2] ; CQI[0] ; CLK        ; CLK      ; None                        ; None                      ; 0.857 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CQI[2] ; CQI[3] ; CLK        ; CLK      ; None                        ; None                      ; 0.856 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; CQI[2] ; CQI[2] ; CLK        ; CLK      ; None                        ; None                      ; 0.852 ns                ;
+-------+------------------------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+


+--------------------------------------------------------------+
; tsu                                                          ;