tenths.edn

watchdog with verilog

(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
(status (written (timeStamp 2007 7 23 12 52 54)
   (author "Xilinx, Inc.")
   (program "Xilinx CORE Generator" (version "Xilinx CORE Generator 9.2.01i"))))
   (comment "                                                                                
      This file is owned and controlled by Xilinx and must be used              
      solely for design, simulation, implementation and creation of             
      design files limited to Xilinx devices or technologies. Use               
      with non-Xilinx devices or technologies is expressly prohibited           
      and immediately terminates your license.                                  
                                                                                
      XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS'             
      SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                   
      XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION           
      AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION               
      OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                 
      IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                   
      AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE          
      FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                  
      WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                   
      IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR            
      REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF           
      INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS           
      FOR A PARTICULAR PURPOSE.                                                 
                                                                                
      Xilinx products are not intended for use in life support                  
      appliances, devices, or systems. Use in such applications are             
      expressly prohibited.                                                     
                                                                                
      (c) Copyright 1995-2007 Xilinx, Inc.                                      
      All rights reserved.                                                      
                                                                                
   ")
   (comment "Core parameters: ")
       (comment "c_count_mode = 0 ")
       (comment "c_has_aset = 0 ")
       (comment "c_load_enable = 0 ")
       (comment "c_load_low = 0 ")
       (comment "c_count_to = 1001 ")
       (comment "c_sync_priority = 1 ")
       (comment "c_has_iv = 0 ")
       (comment "c_has_sclr = 0 ")
       (comment "c_restrict_count = 1 ")
       (comment "c_width = 4 ")
       (comment "c_has_q_thresh1 = 0 ")
       (comment "c_enable_rlocs = 0 ")
       (comment "c_has_q_thresh0 = 0 ")
       (comment "c_thresh1_value = 0 ")
       (comment "c_has_load = 0 ")
       (comment "c_has_up = 0 ")
       (comment "c_thresh_early = 0 ")
       (comment "c_has_thresh1 = 0 ")
       (comment "c_has_thresh0 = 1 ")
       (comment "c_ainit_val = 0 ")
       (comment "c_has_ce = 1 ")
       (comment "c_pipe_stages = 0 ")
       (comment "c_has_aclr = 0 ")
       (comment "InstanceName = tenths ")
       (comment "c_sync_enable = 1 ")
       (comment "c_has_ainit = 1 ")
       (comment "c_sinit_val = 0 ")
       (comment "c_has_sset = 0 ")
       (comment "c_has_sinit = 0 ")
       (comment "c_count_by = 1 ")
       (comment "c_has_l = 0 ")
       (comment "c_thresh0_value = 1001 ")
   (external xilinxun (edifLevel 0)
      (technology (numberDefinition))
       (cell VCC (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port P (direction OUTPUT))
               )
           )
       )
       (cell GND (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port G (direction OUTPUT))
               )
           )
       )
   )
   (external tenths_c_counter_binary_v8_0_xst_1_lib (edifLevel 0)
       (technology (numberDefinition))
       (cell tenths_c_counter_binary_v8_0_xst_1 (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port clk (direction INPUT))
                   (port up (direction INPUT))
                   (port ce (direction INPUT))
                   (port load (direction INPUT))
                   (port ( array ( rename l "l<3:0>") 4 ) (direction INPUT))
                   (port ( array ( rename iv "iv<3:0>") 4 ) (direction INPUT))
                   (port aclr (direction INPUT))
                   (port aset (direction INPUT))
                   (port ainit (direction INPUT))
                   (port sclr (direction INPUT))
                   (port sset (direction INPUT))
                   (port sinit (direction INPUT))
                   (port thresh0 (direction OUTPUT))
                   (port q_thresh0 (direction OUTPUT))
                   (port thresh1 (direction OUTPUT))
                   (port q_thresh1 (direction OUTPUT))
                   (port ( array ( rename q "q<3:0>") 4 ) (direction OUTPUT))
               )
           )
       )
   )
(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))
(cell tenths
 (cellType GENERIC) (view view_1 (viewType NETLIST)
  (interface
   (port ( rename clk "clk") (direction INPUT))
   (port ( rename ce "ce") (direction INPUT))
   (port ( rename ainit "ainit") (direction INPUT))
   (port ( rename thresh0 "thresh0") (direction OUTPUT))
   (port ( array ( rename q "q<3:0>") 4 ) (direction OUTPUT))
   )
  (contents
   (instance VCC (viewRef view_1 (cellRef VCC  (libraryRef xilinxun))))
   (instance GND (viewRef view_1 (cellRef GND  (libraryRef xilinxun))))
   (instance BU2
      (viewRef view_1 (cellRef tenths_c_counter_binary_v8_0_xst_1 (libraryRef tenths_c_counter_binary_v8_0_xst_1_lib)))
   )
   (net (rename N2 "clk")
    (joined
      (portRef clk)
      (portRef clk (instanceRef BU2))
    )
   )
   (net (rename N4 "ce")
    (joined
      (portRef ce)
      (portRef ce (instanceRef BU2))
    )
   )
   (net (rename N16 "ainit")
    (joined
      (portRef ainit)
      (portRef ainit (instanceRef BU2))
    )
   )
   (net (rename N20 "thresh0")
    (joined
      (portRef thresh0)
      (portRef thresh0 (instanceRef BU2))
    )
   )
   (net (rename N24 "q<3>")
    (joined
      (portRef (member q 0))
      (portRef (member q 0) (instanceRef BU2))
    )
   )
   (net (rename N25 "q<2>")
    (joined
      (portRef (member q 1))
      (portRef (member q 1) (instanceRef BU2))
    )
   )
   (net (rename N26 "q<1>")
    (joined
      (portRef (member q 2))
      (portRef (member q 2) (instanceRef BU2))
    )
   )
   (net (rename N27 "q<0>")
    (joined
      (portRef (member q 3))
      (portRef (member q 3) (instanceRef BU2))
    )
   )
))))
(design tenths (cellRef tenths (libraryRef test_lib))
  (property X_CORE_INFO (string "c_counter_binary_v8_0, Coregen 9.2.01i"))
  (property PART (string "xc2vp2-fg256-7") (owner "Xilinx")))
)