stack_te.vhd

来自「Dieses Verzeichnis enthaelt die VHDL-Que」· VHDL 代码 · 共 45 行

-- VHDL Model Created from SGE Schematic stack_test.sch -- Nov 13 11:02:49 1996

library IEEE;
   use IEEE.std_logic_1164.all;
   use IEEE.std_logic_misc.all;
   use IEEE.std_logic_arith.all;
   use IEEE.std_logic_components.all;

entity STACK_TEST is
      Port (     CLK : In    std_logic;
                 DIN : In    std_logic_vector (1 to 12);
                 DIR : In    std_logic;
             RESET_N : In    std_logic;
                DOUT : Out   std_logic_vector (1 to 12) );
end STACK_TEST;

architecture SCHEMATIC of STACK_TEST is


   component STACK
      Port (     CLK : In    std_logic;
                   D : In    std_logic_vector (1 to 12);
                 DIR : In    std_logic;
                  RN : In    std_logic;
                   Q : Out   std_logic_vector (1 to 12) );
   end component;

begin

   I_1 : STACK
      Port Map ( CLK=>CLK, D(1 to 12)=>DIN(1 to 12), DIR=>DIR,
                 RN=>RESET_N, Q(1 to 12)=>DOUT(1 to 12) );

end SCHEMATIC;

configuration CFG_STACK_TEST_SCHEMATIC of STACK_TEST is

   for SCHEMATIC
      for I_1: STACK
         use configuration WORK.CFG_STACK_BEHAVIORAL;
      end for;
   end for;

end CFG_STACK_TEST_SCHEMATIC;