📄 tb_stack.vhd
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-- VHDL Test Bench Created from SGE Symbol stack_test.sym.sym -- Nov 13 11:02:49 1996
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_components.all;
entity E is
end E;
Architecture A of E is
signal CLK : std_logic := '0';
signal DIN : std_logic_vector (1 to 12);
signal DIR : std_logic;
signal RESET_N : std_logic;
signal DOUT : std_logic_vector (1 to 12);
component STACK_TEST
Port ( CLK : In std_logic;
DIN : In std_logic_vector (1 to 12);
DIR : In std_logic;
RESET_N : In std_logic;
DOUT : Out std_logic_vector (1 to 12) );
end component;
begin
UUT : STACK_TEST
Port Map ( CLK, DIN, DIR, RESET_N, DOUT );
-- *** Test Bench - User Defined Section ***
TB : block
begin
CLK <= not(CLK) after 100 ns;
D_STIMULI:process
begin
RESET_N <= '0';
wait for 50 ns;
RESET_N <= '1';
DIR<='1';
DIN<="000000000000";
wait for 200 ns;
DIN<="000000000001" after 10 ns;
wait for 200 ns;
DIN<="000000000010" after 10 ns;
wait for 200 ns;
DIN<="000000000011" after 10 ns;
wait for 200 ns;
DIN<="000000000100" after 10 ns;
wait for 200 ns;
DIN<="000000000101" after 10 ns;
wait for 200 ns;
DIN<="000000000110" after 10 ns;
wait for 200 ns;
DIN<="000000000111" after 10 ns;
wait for 200 ns;
DIN<="000000001000" after 10 ns;
wait for 200 ns;
DIR<='0';
wait for 600 ns;
RESET_N <= '0';
wait ;
end process;
end block;
-- *** End Test Bench - User Defined Section ***
end A;
configuration CFG_TB_STACK_TEST_BEHAVIORAL of E is
for A
for UUT : STACK_TEST
use configuration WORK.CFG_STACK_TEST_SCHEMATIC;
end for;
-- *** User Defined Configuration ***
for TB
end for;
-- *** End User Defined Configuration ***
end for;
end CFG_TB_STACK_TEST_BEHAVIORAL;
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