copy of k163_addition.vhd

elliptic curve in GF2m

----------------------------------------------------------------------------
-- Point Addition in K163 (K163_point_addition.vhd)
--
--
----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
package package_K_163 is
  constant m: natural := 163;
  constant logm: natural := 8;
end package_K_163;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.package_K_163.all;

------------------------------------------------------------
-- K163_point_addition
------------------------------------------------------------
entity K163_addition is
port(
  x1, y1, x2, y2: in std_logic_vector(m-1 downto 0);
  clk, reset, start: in std_logic;
  x3: inout std_logic_vector(m-1 downto 0);
  y3: out std_logic_vector(m-1 downto 0);
  done: out std_logic
  );
end K163_addition;

architecture circuit of K163_addition is
  component interleaved_mult is
  port (
    A, B: in std_logic_vector (M-1 downto 0);
    clk, reset, start: in std_logic; 
    Z: out std_logic_vector (M-1 downto 0);
    done: out std_logic );
  end component;
  component binary_algorithm_polynomials is
  port(
    g, h: in std_logic_vector(m-1 downto 0);
    clk, reset, start: in std_logic;  
    z: out std_logic_vector(m-1 downto 0);
    done: out std_logic );
  end component;

  --component square_163_7_6_3 is
  --port (
  --a: in std_logic_vector(162 downto 0);
  --z: out std_logic_vector(162 downto 0)
  --);
  --end component;

  component classic_squarer is
  port (
    a: in std_logic_vector(M-1 downto 0);
    c: out std_logic_vector(M-1 downto 0));
  end component;

  signal div_in1, div_in2, lambda, lambda_square, 
  mult_in2, mult_out: std_logic_vector(m-1 downto 0);
  signal start_div, div_done, start_mult, mult_done: std_logic;
  subtype states is natural range 0 to 6;
  signal current_state: states;

begin

  divider_inputs: for i in 0 to m-1 generate 
    div_in1(i) <= y1(i) xor y2(i);
    div_in2(i) <= x1(i) xor x2(i);
  end generate;

  divider: binary_algorithm_polynomials port map( g => div_in1, h => div_in2, 
                              clk => clk, reset => reset, start => start_div, 
                              z => lambda, done => div_done);

  lambda_square_computation: classic_squarer port map( a => lambda, c => lambda_square);

  x_output: for i in 1 to 162 generate
    x3(i) <= lambda_square(i) xor lambda(i) xor div_in2(i);
  end generate;

  x3(0) <= not(lambda_square(0) xor lambda(0) xor div_in2(0));

  multiplier_inputs: for i in 0 to 162 generate
    mult_in2(i) <= x1(i) xor x3(i);
  end generate;

  multiplier: interleaved_mult port map( a => lambda, b => mult_in2, 
                    clk => clk, reset => reset, start => start_mult, 
                    z => mult_out, done => mult_done);

  y_output: for i in 0 to 162 generate
    y3(i) <= mult_out(i) xor x3(i) xor y1(i);
  end generate;

  control_unit: process(clk, reset, current_state)
  begin
  case current_state is
    when 0 to 1 => start_div <= '0'; start_mult <= '0'; done <= '1';
    when 2 => start_div <= '1'; start_mult <= '0'; done <= '0';
    when 3 => start_div <= '0'; start_mult <= '0'; done <= '0';
    when 4 => start_div <= '0'; start_mult <= '1'; done <= '0';
    when 5 to 6 => start_div <= '0'; start_mult <= '0'; done <= '0';
  end case;

  if reset = '1' then current_state <= 0;
  elsif clk'event and clk = '1' then
    case current_state is
      when 0 => if start = '0' then current_state <= 1; end if;
      when 1 => if start = '1' then current_state <= 2; end if; 
      when 2 => current_state <= 3;
      when 3 => if div_done = '1' then current_state <= 4; end if;
      when 4 => current_state <= 5;
      when 5 => if mult_done = '1' then current_state <= 6; end if;
      when 6 => current_state <= 0;
    end case;
  end if;
  end process;
end circuit;