pwm.fit.qmsg

实现PWM波的产生,可用于电机控制.可以改变其占空比及频率来实现电机的调速.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.1 Build 163 10/28/2008 SJ Full Version " "Info: Version 8.1 Build 163 10/28/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 25 13:04:54 2009 " "Info: Processing started: Mon May 25 13:04:54 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off PWM -c PWM " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off PWM -c PWM" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "PWM EP2C8T144C8 " "Info: Selected device EP2C8T144C8 for design \"PWM\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 0}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" {  } {  } 0 0 "%1!s! is %2!s!" 0 0 "" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5T144C8 " "Info: Device EP2C5T144C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5T144I8 " "Info: Device EP2C5T144I8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8T144I8 " "Info: Device EP2C8T144I8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 0}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" {  } { { "f:/quartus/bin/pin_planner.ppl" "" { PinPlanner "f:/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" {  } { { "f:/quartus/bin/pin_planner.ppl" "" { PinPlanner "f:/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS54p/nCEO~ 76 " "Info: Pin ~LVDS54p/nCEO~ is reserved at location 76" {  } { { "f:/quartus/bin/pin_planner.ppl" "" { PinPlanner "f:/quartus/bin/pin_planner.ppl" { ~LVDS54p/nCEO~ } } } { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS54p/nCEO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 0}
{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "3 6 " "Warning: No exact pin location assignment(s) for 3 pins of 6 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "conv " "Info: Pin conv not assigned to an exact location on the device" {  } { { "f:/quartus/bin/pin_planner.ppl" "" { PinPlanner "f:/quartus/bin/pin_planner.ppl" { conv } } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 6 -1 0 } } { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "" { conv } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "sub " "Info: Pin sub not assigned to an exact location on the device" {  } { { "f:/quartus/bin/pin_planner.ppl" "" { PinPlanner "f:/quartus/bin/pin_planner.ppl" { sub } } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 6 -1 0 } } { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "" { sub } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "add " "Info: Pin add not assigned to an exact location on the device" {  } { { "f:/quartus/bin/pin_planner.ppl" "" { PinPlanner "f:/quartus/bin/pin_planner.ppl" { add } } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 6 -1 0 } } { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "" { add } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 0}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 0}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." {  } {  } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk (placed in PIN 91 (CLK4, LVDSCLK2p, Input)) " "Info: Automatically promoted node clk (placed in PIN 91 (CLK4, LVDSCLK2p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G6 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G6" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "clkout " "Info: Destination node clkout" {  } { { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 41 -1 0 } } { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkout } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 0}  } { { "f:/quartus/bin/pin_planner.ppl" "" { PinPlanner "f:/quartus/bin/pin_planner.ppl" { clk } } } { "f:/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 6 -1 0 } } { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clkout  " "Info: Automatically promoted node clkout " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "clkout~220 " "Info: Destination node clkout~220" {  } { { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 41 -1 0 } } { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkout~220 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 0}  } { { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 41 -1 0 } } { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkout } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "reset (placed in PIN 90 (CLK5, LVDSCLK2n, Input)) " "Info: Automatically promoted node reset (placed in PIN 90 (CLK5, LVDSCLK2n, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G5 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G5" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "bout~155 " "Info: Destination node bout~155" {  } { { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 6 -1 0 } } { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "" { bout~155 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 0}  } { { "f:/quartus/bin/pin_planner.ppl" "" { PinPlanner "f:/quartus/bin/pin_planner.ppl" { reset } } } { "f:/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/quartus/bin/Assignment Editor.qase" 1 { { 0 "reset" } } } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 6 -1 0 } } { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 0}