prev_cmp_pwm.map.qmsg

实现PWM波的产生,可用于电机控制.可以改变其占空比及频率来实现电机的调速.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.1 Build 163 10/28/2008 SJ Full Version " "Info: Version 8.1 Build 163 10/28/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 25 13:04:01 2009 " "Info: Processing started: Mon May 25 13:04:01 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off PWM -c PWM " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off PWM -c PWM" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "PWM.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file PWM.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 PWM-Behavioral " "Info: Found design unit 1: PWM-Behavioral" {  } { { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 PWM " "Info: Found entity 1: PWM" {  } { { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "PWM " "Info: Elaborating entity \"PWM\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "bclk0 PWM.vhd(56) " "Warning (10036): Verilog HDL or VHDL warning at PWM.vhd(56): object \"bclk0\" assigned a value but never read" {  } { { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 56 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 41 -1 0 } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 18 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0 0}
{ "Critical Warning" "WFTM_FTM_POWER_UP_HIGH_IGNORED_GROUP" "" "Critical Warning: Ignored Power-Up Level option on the following registers" { { "Critical Warning" "WFTM_FTM_CORE_REG_POWER_UP_HIGH_IGNORED" "H\[5\] High " "Critical Warning: Register H\[5\] will power up to High" {  } { { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 18 -1 0 } }  } 1 0 "Register %1!s! will power up to %2!s!" 0 0 "" 0 0} { "Critical Warning" "WFTM_FTM_CORE_REG_POWER_UP_HIGH_IGNORED" "H\[4\] High " "Critical Warning: Register H\[4\] will power up to High" {  } { { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 18 -1 0 } }  } 1 0 "Register %1!s! will power up to %2!s!" 0 0 "" 0 0} { "Critical Warning" "WFTM_FTM_CORE_REG_POWER_UP_HIGH_IGNORED" "H\[1\] High " "Critical Warning: Register H\[1\] will power up to High" {  } { { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 18 -1 0 } }  } 1 0 "Register %1!s! will power up to %2!s!" 0 0 "" 0 0} { "Critical Warning" "WFTM_FTM_CORE_REG_POWER_UP_HIGH_IGNORED" "ss\[0\] High " "Critical Warning: Register ss\[0\] will power up to High" {  } { { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 18 -1 0 } }  } 1 0 "Register %1!s! will power up to %2!s!" 0 0 "" 0 0}  } {  } 1 0 "Ignored Power-Up Level option on the following registers" 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "82 " "Info: Implemented 82 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "76 " "Info: Implemented 76 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "187 " "Info: Peak virtual memory: 187 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 25 13:04:04 2009 " "Info: Processing ended: Mon May 25 13:04:04 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}