prev_cmp_pwm.tan.qmsg

实现PWM波的产生,可用于电机控制.可以改变其占空比及频率来实现电机的调速.

{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "H\[6\] bout~reg0 clk 3.062 ns " "Info: Found hold time violation between source  pin or register \"H\[6\]\" and destination pin or register \"bout~reg0\" for clock \"clk\" (Hold time is 3.062 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "5.438 ns + Largest " "Info: + Largest clock skew is 5.438 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.261 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 8.261 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_91 2 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_91; Fanout = 2; CLK Node = 'clk'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.963 ns) + CELL(0.970 ns) 4.033 ns clkout 2 REG LCFF_X16_Y4_N9 2 " "Info: 2: + IC(1.963 ns) + CELL(0.970 ns) = 4.033 ns; Loc. = LCFF_X16_Y4_N9; Fanout = 2; REG Node = 'clkout'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "2.933 ns" { clk clkout } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.645 ns) + CELL(0.000 ns) 6.678 ns clkout~clkctrl 3 COMB CLKCTRL_G3 8 " "Info: 3: + IC(2.645 ns) + CELL(0.000 ns) = 6.678 ns; Loc. = CLKCTRL_G3; Fanout = 8; COMB Node = 'clkout~clkctrl'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "2.645 ns" { clkout clkout~clkctrl } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.917 ns) + CELL(0.666 ns) 8.261 ns bout~reg0 4 REG LCFF_X8_Y5_N25 2 " "Info: 4: + IC(0.917 ns) + CELL(0.666 ns) = 8.261 ns; Loc. = LCFF_X8_Y5_N25; Fanout = 2; REG Node = 'bout~reg0'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "1.583 ns" { clkout~clkctrl bout~reg0 } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 58 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.736 ns ( 33.12 % ) " "Info: Total cell delay = 2.736 ns ( 33.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.525 ns ( 66.88 % ) " "Info: Total interconnect delay = 5.525 ns ( 66.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "8.261 ns" { clk clkout clkout~clkctrl bout~reg0 } "NODE_NAME" } } { "f:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartus/bin/Technology_Viewer.qrui" "8.261 ns" { clk {} clk~combout {} clkout {} clkout~clkctrl {} bout~reg0 {} } { 0.000ns 0.000ns 1.963ns 2.645ns 0.917ns } { 0.000ns 1.100ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.823 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 2.823 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_91 2 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_91; Fanout = 2; CLK Node = 'clk'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.239 ns clk~clkctrl 2 COMB CLKCTRL_G6 22 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.239 ns; Loc. = CLKCTRL_G6; Fanout = 22; COMB Node = 'clk~clkctrl'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.918 ns) + CELL(0.666 ns) 2.823 ns H\[6\] 3 REG LCFF_X9_Y5_N31 2 " "Info: 3: + IC(0.918 ns) + CELL(0.666 ns) = 2.823 ns; Loc. = LCFF_X9_Y5_N31; Fanout = 2; REG Node = 'H\[6\]'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "1.584 ns" { clk~clkctrl H[6] } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.766 ns ( 62.56 % ) " "Info: Total cell delay = 1.766 ns ( 62.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.057 ns ( 37.44 % ) " "Info: Total interconnect delay = 1.057 ns ( 37.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "2.823 ns" { clk clk~clkctrl H[6] } "NODE_NAME" } } { "f:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartus/bin/Technology_Viewer.qrui" "2.823 ns" { clk {} clk~combout {} clk~clkctrl {} H[6] {} } { 0.000ns 0.000ns 0.139ns 0.918ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "8.261 ns" { clk clkout clkout~clkctrl bout~reg0 } "NODE_NAME" } } { "f:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartus/bin/Technology_Viewer.qrui" "8.261 ns" { clk {} clk~combout {} clkout {} clkout~clkctrl {} bout~reg0 {} } { 0.000ns 0.000ns 1.963ns 2.645ns 0.917ns } { 0.000ns 1.100ns 0.970ns 0.000ns 0.666ns } "" } } { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "2.823 ns" { clk clk~clkctrl H[6] } "NODE_NAME" } } { "f:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartus/bin/Technology_Viewer.qrui" "2.823 ns" { clk {} clk~combout {} clk~clkctrl {} H[6] {} } { 0.000ns 0.000ns 0.139ns 0.918ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" {  } { { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.378 ns - Shortest register register " "Info: - Shortest register to register delay is 2.378 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns H\[6\] 1 REG LCFF_X9_Y5_N31 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X9_Y5_N31; Fanout = 2; REG Node = 'H\[6\]'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "" { H[6] } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.440 ns) + CELL(0.624 ns) 1.064 ns LessThan2~103 2 COMB LCCOMB_X9_Y5_N14 1 " "Info: 2: + IC(0.440 ns) + CELL(0.624 ns) = 1.064 ns; Loc. = LCCOMB_X9_Y5_N14; Fanout = 1; COMB Node = 'LessThan2~103'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "1.064 ns" { H[6] LessThan2~103 } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.582 ns) + CELL(0.624 ns) 2.270 ns bout~155 3 COMB LCCOMB_X8_Y5_N24 1 " "Info: 3: + IC(0.582 ns) + CELL(0.624 ns) = 2.270 ns; Loc. = LCCOMB_X8_Y5_N24; Fanout = 1; COMB Node = 'bout~155'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "1.206 ns" { LessThan2~103 bout~155 } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 2.378 ns bout~reg0 4 REG LCFF_X8_Y5_N25 2 " "Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 2.378 ns; Loc. = LCFF_X8_Y5_N25; Fanout = 2; REG Node = 'bout~reg0'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { bout~155 bout~reg0 } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 58 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.356 ns ( 57.02 % ) " "Info: Total cell delay = 1.356 ns ( 57.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.022 ns ( 42.98 % ) " "Info: Total interconnect delay = 1.022 ns ( 42.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "2.378 ns" { H[6] LessThan2~103 bout~155 bout~reg0 } "NODE_NAME" } } { "f:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartus/bin/Technology_Viewer.qrui" "2.378 ns" { H[6] {} LessThan2~103 {} bout~155 {} bout~reg0 {} } { 0.000ns 0.440ns 0.582ns 0.000ns } { 0.000ns 0.624ns 0.624ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 58 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 18 -1 0 } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 58 0 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0 0}  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "8.261 ns" { clk clkout clkout~clkctrl bout~reg0 } "NODE_NAME" } } { "f:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartus/bin/Technology_Viewer.qrui" "8.261 ns" { clk {} clk~combout {} clkout {} clkout~clkctrl {} bout~reg0 {} } { 0.000ns 0.000ns 1.963ns 2.645ns 0.917ns } { 0.000ns 1.100ns 0.970ns 0.000ns 0.666ns } "" } } { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "2.823 ns" { clk clk~clkctrl H[6] } "NODE_NAME" } } { "f:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartus/bin/Technology_Viewer.qrui" "2.823 ns" { clk {} clk~combout {} clk~clkctrl {} H[6] {} } { 0.000ns 0.000ns 0.139ns 0.918ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } } { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "2.378 ns" { H[6] LessThan2~103 bout~155 bout~reg0 } "NODE_NAME" } } { "f:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartus/bin/Technology_Viewer.qrui" "2.378 ns" { H[6] {} LessThan2~103 {} bout~155 {} bout~reg0 {} } { 0.000ns 0.440ns 0.582ns 0.000ns } { 0.000ns 0.624ns 0.624ns 0.108ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "H\[5\] conv clk 9.201 ns register " "Info: tsu for register \"H\[5\]\" (data pin = \"conv\", clock pin = \"clk\") is 9.201 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.074 ns + Longest pin register " "Info: + Longest pin to register delay is 12.074 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns conv 1 PIN PIN_52 7 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_52; Fanout = 7; PIN Node = 'conv'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "" { conv } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.932 ns) + CELL(0.651 ns) 8.517 ns Add0~150 2 COMB LCCOMB_X9_Y5_N16 2 " "Info: 2: + IC(6.932 ns) + CELL(0.651 ns) = 8.517 ns; Loc. = LCCOMB_X9_Y5_N16; Fanout = 2; COMB Node = 'Add0~150'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "7.583 ns" { conv Add0~150 } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.395 ns) + CELL(0.621 ns) 9.533 ns Add0~152 3 COMB LCCOMB_X9_Y5_N18 2 " "Info: 3: + IC(0.395 ns) + CELL(0.621 ns) = 9.533 ns; Loc. = LCCOMB_X9_Y5_N18; Fanout = 2; COMB Node = 'Add0~152'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "1.016 ns" { Add0~150 Add0~152 } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 9.619 ns Add0~154 4 COMB LCCOMB_X9_Y5_N20 2 " "Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 9.619 ns; Loc. = LCCOMB_X9_Y5_N20; Fanout = 2; COMB Node = 'Add0~154'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~152 Add0~154 } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 9.705 ns Add0~156 5 COMB LCCOMB_X9_Y5_N22 2 " "Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 9.705 ns; Loc. = LCCOMB_X9_Y5_N22; Fanout = 2; COMB Node = 'Add0~156'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~154 Add0~156 } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 9.791 ns Add0~158 6 COMB LCCOMB_X9_Y5_N24 2 " "Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 9.791 ns; Loc. = LCCOMB_X9_Y5_N24; Fanout = 2; COMB Node = 'Add0~158'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~156 Add0~158 } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 9.877 ns Add0~160 7 COMB LCCOMB_X9_Y5_N26 2 " "Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 9.877 ns; Loc. = LCCOMB_X9_Y5_N26; Fanout = 2; COMB Node = 'Add0~160'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~158 Add0~160 } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 10.383 ns Add0~161 8 COMB LCCOMB_X9_Y5_N28 1 " "Info: 8: + IC(0.000 ns) + CELL(0.506 ns) = 10.383 ns; Loc. = LCCOMB_X9_Y5_N28; Fanout = 1; COMB Node = 'Add0~161'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { Add0~160 Add0~161 } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.381 ns) + CELL(0.202 ns) 11.966 ns H\[5\]~231 9 COMB LCCOMB_X14_Y5_N24 1 " "Info: 9: + IC(1.381 ns) + CELL(0.202 ns) = 11.966 ns; Loc. = LCCOMB_X14_Y5_N24; Fanout = 1; COMB Node = 'H\[5\]~231'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "1.583 ns" { Add0~161 H[5]~231 } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 12.074 ns H\[5\] 10 REG LCFF_X14_Y5_N25 3 " "Info: 10: + IC(0.000 ns) + CELL(0.108 ns) = 12.074 ns; Loc. = LCFF_X14_Y5_N25; Fanout = 3; REG Node = 'H\[5\]'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { H[5]~231 H[5] } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.366 ns ( 27.88 % ) " "Info: Total cell delay = 3.366 ns ( 27.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.708 ns ( 72.12 % ) " "Info: Total interconnect delay = 8.708 ns ( 72.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "12.074 ns" { conv Add0~150 Add0~152 Add0~154 Add0~156 Add0~158 Add0~160 Add0~161 H[5]~231 H[5] } "NODE_NAME" } } { "f:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartus/bin/Technology_Viewer.qrui" "12.074 ns" { conv {} conv~combout {} Add0~150 {} Add0~152 {} Add0~154 {} Add0~156 {} Add0~158 {} Add0~160 {} Add0~161 {} H[5]~231 {} H[5] {} } { 0.000ns 0.000ns 6.932ns 0.395ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.381ns 0.000ns } { 0.000ns 0.934ns 0.651ns 0.621ns 0.086ns 0.086ns 0.086ns 0.086ns 0.506ns 0.202ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.833 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.833 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_91 2 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_91; Fanout = 2; CLK Node = 'clk'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.239 ns clk~clkctrl 2 COMB CLKCTRL_G6 22 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.239 ns; Loc. = CLKCTRL_G6; Fanout = 22; COMB Node = 'clk~clkctrl'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.928 ns) + CELL(0.666 ns) 2.833 ns H\[5\] 3 REG LCFF_X14_Y5_N25 3 " "Info: 3: + IC(0.928 ns) + CELL(0.666 ns) = 2.833 ns; Loc. = LCFF_X14_Y5_N25; Fanout = 3; REG Node = 'H\[5\]'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "1.594 ns" { clk~clkctrl H[5] } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.766 ns ( 62.34 % ) " "Info: Total cell delay = 1.766 ns ( 62.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.067 ns ( 37.66 % ) " "Info: Total interconnect delay = 1.067 ns ( 37.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "2.833 ns" { clk clk~clkctrl H[5] } "NODE_NAME" } } { "f:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartus/bin/Technology_Viewer.qrui" "2.833 ns" { clk {} clk~combout {} clk~clkctrl {} H[5] {} } { 0.000ns 0.000ns 0.139ns 0.928ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "12.074 ns" { conv Add0~150 Add0~152 Add0~154 Add0~156 Add0~158 Add0~160 Add0~161 H[5]~231 H[5] } "NODE_NAME" } } { "f:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartus/bin/Technology_Viewer.qrui" "12.074 ns" { conv {} conv~combout {} Add0~150 {} Add0~152 {} Add0~154 {} Add0~156 {} Add0~158 {} Add0~160 {} Add0~161 {} H[5]~231 {} H[5] {} } { 0.000ns 0.000ns 6.932ns 0.395ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.381ns 0.000ns } { 0.000ns 0.934ns 0.651ns 0.621ns 0.086ns 0.086ns 0.086ns 0.086ns 0.506ns 0.202ns 0.108ns } "" } } { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "2.833 ns" { clk clk~clkctrl H[5] } "NODE_NAME" } } { "f:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartus/bin/Technology_Viewer.qrui" "2.833 ns" { clk {} clk~combout {} clk~clkctrl {} H[5] {} } { 0.000ns 0.000ns 0.139ns 0.928ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk bout bout~reg0 14.503 ns register " "Info: tco from clock \"clk\" to destination pin \"bout\" through register \"bout~reg0\" is 14.503 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.261 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 8.261 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_91 2 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_91; Fanout = 2; CLK Node = 'clk'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.963 ns) + CELL(0.970 ns) 4.033 ns clkout 2 REG LCFF_X16_Y4_N9 2 " "Info: 2: + IC(1.963 ns) + CELL(0.970 ns) = 4.033 ns; Loc. = LCFF_X16_Y4_N9; Fanout = 2; REG Node = 'clkout'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "2.933 ns" { clk clkout } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.645 ns) + CELL(0.000 ns) 6.678 ns clkout~clkctrl 3 COMB CLKCTRL_G3 8 " "Info: 3: + IC(2.645 ns) + CELL(0.000 ns) = 6.678 ns; Loc. = CLKCTRL_G3; Fanout = 8; COMB Node = 'clkout~clkctrl'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "2.645 ns" { clkout clkout~clkctrl } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.917 ns) + CELL(0.666 ns) 8.261 ns bout~reg0 4 REG LCFF_X8_Y5_N25 2 " "Info: 4: + IC(0.917 ns) + CELL(0.666 ns) = 8.261 ns; Loc. = LCFF_X8_Y5_N25; Fanout = 2; REG Node = 'bout~reg0'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "1.583 ns" { clkout~clkctrl bout~reg0 } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 58 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.736 ns ( 33.12 % ) " "Info: Total cell delay = 2.736 ns ( 33.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.525 ns ( 66.88 % ) " "Info: Total interconnect delay = 5.525 ns ( 66.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "8.261 ns" { clk clkout clkout~clkctrl bout~reg0 } "NODE_NAME" } } { "f:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartus/bin/Technology_Viewer.qrui" "8.261 ns" { clk {} clk~combout {} clkout {} clkout~clkctrl {} bout~reg0 {} } { 0.000ns 0.000ns 1.963ns 2.645ns 0.917ns } { 0.000ns 1.100ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 58 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.938 ns + Longest register pin " "Info: + Longest register to pin delay is 5.938 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns bout~reg0 1 REG LCFF_X8_Y5_N25 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X8_Y5_N25; Fanout = 2; REG Node = 'bout~reg0'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "" { bout~reg0 } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 58 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.882 ns) + CELL(3.056 ns) 5.938 ns bout 2 PIN PIN_4 0 " "Info: 2: + IC(2.882 ns) + CELL(3.056 ns) = 5.938 ns; Loc. = PIN_4; Fanout = 0; PIN Node = 'bout'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "5.938 ns" { bout~reg0 bout } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.056 ns ( 51.47 % ) " "Info: Total cell delay = 3.056 ns ( 51.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.882 ns ( 48.53 % ) " "Info: Total interconnect delay = 2.882 ns ( 48.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "5.938 ns" { bout~reg0 bout } "NODE_NAME" } } { "f:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartus/bin/Technology_Viewer.qrui" "5.938 ns" { bout~reg0 {} bout {} } { 0.000ns 2.882ns } { 0.000ns 3.056ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "8.261 ns" { clk clkout clkout~clkctrl bout~reg0 } "NODE_NAME" } } { "f:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartus/bin/Technology_Viewer.qrui" "8.261 ns" { clk {} clk~combout {} clkout {} clkout~clkctrl {} bout~reg0 {} } { 0.000ns 0.000ns 1.963ns 2.645ns 0.917ns } { 0.000ns 1.100ns 0.970ns 0.000ns 0.666ns } "" } } { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "5.938 ns" { bout~reg0 bout } "NODE_NAME" } } { "f:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartus/bin/Technology_Viewer.qrui" "5.938 ns" { bout~reg0 {} bout {} } { 0.000ns 2.882ns } { 0.000ns 3.056ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "bout~reg0 reset clk 4.031 ns register " "Info: th for register \"bout~reg0\" (data pin = \"reset\", clock pin = \"clk\") is 4.031 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.261 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 8.261 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_91 2 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_91; Fanout = 2; CLK Node = 'clk'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.963 ns) + CELL(0.970 ns) 4.033 ns clkout 2 REG LCFF_X16_Y4_N9 2 " "Info: 2: + IC(1.963 ns) + CELL(0.970 ns) = 4.033 ns; Loc. = LCFF_X16_Y4_N9; Fanout = 2; REG Node = 'clkout'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "2.933 ns" { clk clkout } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.645 ns) + CELL(0.000 ns) 6.678 ns clkout~clkctrl 3 COMB CLKCTRL_G3 8 " "Info: 3: + IC(2.645 ns) + CELL(0.000 ns) = 6.678 ns; Loc. = CLKCTRL_G3; Fanout = 8; COMB Node = 'clkout~clkctrl'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "2.645 ns" { clkout clkout~clkctrl } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.917 ns) + CELL(0.666 ns) 8.261 ns bout~reg0 4 REG LCFF_X8_Y5_N25 2 " "Info: 4: + IC(0.917 ns) + CELL(0.666 ns) = 8.261 ns; Loc. = LCFF_X8_Y5_N25; Fanout = 2; REG Node = 'bout~reg0'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "1.583 ns" { clkout~clkctrl bout~reg0 } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 58 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.736 ns ( 33.12 % ) " "Info: Total cell delay = 2.736 ns ( 33.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.525 ns ( 66.88 % ) " "Info: Total interconnect delay = 5.525 ns ( 66.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "8.261 ns" { clk clkout clkout~clkctrl bout~reg0 } "NODE_NAME" } } { "f:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartus/bin/Technology_Viewer.qrui" "8.261 ns" { clk {} clk~combout {} clkout {} clkout~clkctrl {} bout~reg0 {} } { 0.000ns 0.000ns 1.963ns 2.645ns 0.917ns } { 0.000ns 1.100ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 58 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.536 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.536 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns reset 1 PIN PIN_90 2 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_90; Fanout = 2; PIN Node = 'reset'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.678 ns) + CELL(0.650 ns) 4.428 ns bout~155 2 COMB LCCOMB_X8_Y5_N24 1 " "Info: 2: + IC(2.678 ns) + CELL(0.650 ns) = 4.428 ns; Loc. = LCCOMB_X8_Y5_N24; Fanout = 1; COMB Node = 'bout~155'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "3.328 ns" { reset bout~155 } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 4.536 ns bout~reg0 3 REG LCFF_X8_Y5_N25 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 4.536 ns; Loc. = LCFF_X8_Y5_N25; Fanout = 2; REG Node = 'bout~reg0'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { bout~155 bout~reg0 } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 58 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.858 ns ( 40.96 % ) " "Info: Total cell delay = 1.858 ns ( 40.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.678 ns ( 59.04 % ) " "Info: Total interconnect delay = 2.678 ns ( 59.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "4.536 ns" { reset bout~155 bout~reg0 } "NODE_NAME" } } { "f:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartus/bin/Technology_Viewer.qrui" "4.536 ns" { reset {} reset~combout {} bout~155 {} bout~reg0 {} } { 0.000ns 0.000ns 2.678ns 0.000ns } { 0.000ns 1.100ns 0.650ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "8.261 ns" { clk clkout clkout~clkctrl bout~reg0 } "NODE_NAME" } } { "f:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartus/bin/Technology_Viewer.qrui" "8.261 ns" { clk {} clk~combout {} clkout {} clkout~clkctrl {} bout~reg0 {} } { 0.000ns 0.000ns 1.963ns 2.645ns 0.917ns } { 0.000ns 1.100ns 0.970ns 0.000ns 0.666ns } "" } } { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "4.536 ns" { reset bout~155 bout~reg0 } "NODE_NAME" } } { "f:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartus/bin/Technology_Viewer.qrui" "4.536 ns" { reset {} reset~combout {} bout~155 {} bout~reg0 {} } { 0.000ns 0.000ns 2.678ns 0.000ns } { 0.000ns 1.100ns 0.650ns 0.108ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}