prev_cmp_pwm.tan.qmsg

实现PWM波的产生,可用于电机控制.可以改变其占空比及频率来实现电机的调速.

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 6 -1 0 } } { "f:/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clkout " "Info: Detected ripple clock \"clkout\" as buffer" {  } { { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 41 -1 0 } } { "f:/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clkout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register ss\[0\] register clkout 168.46 MHz 5.936 ns Internal " "Info: Clock \"clk\" has Internal fmax of 168.46 MHz between source register \"ss\[0\]\" and destination register \"clkout\" (period= 5.936 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.576 ns + Longest register register " "Info: + Longest register to register delay is 6.576 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ss\[0\] 1 REG LCFF_X10_Y5_N3 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X10_Y5_N3; Fanout = 7; REG Node = 'ss\[0\]'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "" { ss[0] } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.887 ns) + CELL(0.706 ns) 2.593 ns Add4~109 2 COMB LCCOMB_X16_Y4_N14 2 " "Info: 2: + IC(1.887 ns) + CELL(0.706 ns) = 2.593 ns; Loc. = LCCOMB_X16_Y4_N14; Fanout = 2; COMB Node = 'Add4~109'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "2.593 ns" { ss[0] Add4~109 } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.679 ns Add4~111 3 COMB LCCOMB_X16_Y4_N16 2 " "Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 2.679 ns; Loc. = LCCOMB_X16_Y4_N16; Fanout = 2; COMB Node = 'Add4~111'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add4~109 Add4~111 } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.765 ns Add4~113 4 COMB LCCOMB_X16_Y4_N18 2 " "Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 2.765 ns; Loc. = LCCOMB_X16_Y4_N18; Fanout = 2; COMB Node = 'Add4~113'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add4~111 Add4~113 } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.851 ns Add4~115 5 COMB LCCOMB_X16_Y4_N20 2 " "Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 2.851 ns; Loc. = LCCOMB_X16_Y4_N20; Fanout = 2; COMB Node = 'Add4~115'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add4~113 Add4~115 } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 3.357 ns Add4~116 6 COMB LCCOMB_X16_Y4_N22 3 " "Info: 6: + IC(0.000 ns) + CELL(0.506 ns) = 3.357 ns; Loc. = LCCOMB_X16_Y4_N22; Fanout = 3; COMB Node = 'Add4~116'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { Add4~115 Add4~116 } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.134 ns) + CELL(0.651 ns) 5.142 ns LessThan1~406 7 COMB LCCOMB_X17_Y4_N24 1 " "Info: 7: + IC(1.134 ns) + CELL(0.651 ns) = 5.142 ns; Loc. = LCCOMB_X17_Y4_N24; Fanout = 1; COMB Node = 'LessThan1~406'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "1.785 ns" { Add4~116 LessThan1~406 } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.710 ns) + CELL(0.616 ns) 6.468 ns clkout~220 8 COMB LCCOMB_X16_Y4_N8 1 " "Info: 8: + IC(0.710 ns) + CELL(0.616 ns) = 6.468 ns; Loc. = LCCOMB_X16_Y4_N8; Fanout = 1; COMB Node = 'clkout~220'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "1.326 ns" { LessThan1~406 clkout~220 } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 6.576 ns clkout 9 REG LCFF_X16_Y4_N9 2 " "Info: 9: + IC(0.000 ns) + CELL(0.108 ns) = 6.576 ns; Loc. = LCFF_X16_Y4_N9; Fanout = 2; REG Node = 'clkout'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { clkout~220 clkout } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.845 ns ( 43.26 % ) " "Info: Total cell delay = 2.845 ns ( 43.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.731 ns ( 56.74 % ) " "Info: Total interconnect delay = 3.731 ns ( 56.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "6.576 ns" { ss[0] Add4~109 Add4~111 Add4~113 Add4~115 Add4~116 LessThan1~406 clkout~220 clkout } "NODE_NAME" } } { "f:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartus/bin/Technology_Viewer.qrui" "6.576 ns" { ss[0] {} Add4~109 {} Add4~111 {} Add4~113 {} Add4~115 {} Add4~116 {} LessThan1~406 {} clkout~220 {} clkout {} } { 0.000ns 1.887ns 0.000ns 0.000ns 0.000ns 0.000ns 1.134ns 0.710ns 0.000ns } { 0.000ns 0.706ns 0.086ns 0.086ns 0.086ns 0.506ns 0.651ns 0.616ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.904 ns - Smallest " "Info: - Smallest clock skew is 0.904 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.729 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.729 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_91 2 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_91; Fanout = 2; CLK Node = 'clk'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.963 ns) + CELL(0.666 ns) 3.729 ns clkout 2 REG LCFF_X16_Y4_N9 2 " "Info: 2: + IC(1.963 ns) + CELL(0.666 ns) = 3.729 ns; Loc. = LCFF_X16_Y4_N9; Fanout = 2; REG Node = 'clkout'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "2.629 ns" { clk clkout } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.766 ns ( 47.36 % ) " "Info: Total cell delay = 1.766 ns ( 47.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.963 ns ( 52.64 % ) " "Info: Total interconnect delay = 1.963 ns ( 52.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "3.729 ns" { clk clkout } "NODE_NAME" } } { "f:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartus/bin/Technology_Viewer.qrui" "3.729 ns" { clk {} clk~combout {} clkout {} } { 0.000ns 0.000ns 1.963ns } { 0.000ns 1.100ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.825 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.825 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns clk 1 CLK PIN_91 2 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_91; Fanout = 2; CLK Node = 'clk'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.239 ns clk~clkctrl 2 COMB CLKCTRL_G6 22 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.239 ns; Loc. = CLKCTRL_G6; Fanout = 22; COMB Node = 'clk~clkctrl'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.920 ns) + CELL(0.666 ns) 2.825 ns ss\[0\] 3 REG LCFF_X10_Y5_N3 7 " "Info: 3: + IC(0.920 ns) + CELL(0.666 ns) = 2.825 ns; Loc. = LCFF_X10_Y5_N3; Fanout = 7; REG Node = 'ss\[0\]'" {  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "1.586 ns" { clk~clkctrl ss[0] } "NODE_NAME" } } { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.766 ns ( 62.51 % ) " "Info: Total cell delay = 1.766 ns ( 62.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.059 ns ( 37.49 % ) " "Info: Total interconnect delay = 1.059 ns ( 37.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "2.825 ns" { clk clk~clkctrl ss[0] } "NODE_NAME" } } { "f:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartus/bin/Technology_Viewer.qrui" "2.825 ns" { clk {} clk~combout {} clk~clkctrl {} ss[0] {} } { 0.000ns 0.000ns 0.139ns 0.920ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "3.729 ns" { clk clkout } "NODE_NAME" } } { "f:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartus/bin/Technology_Viewer.qrui" "3.729 ns" { clk {} clk~combout {} clkout {} } { 0.000ns 0.000ns 1.963ns } { 0.000ns 1.100ns 0.666ns } "" } } { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "2.825 ns" { clk clk~clkctrl ss[0] } "NODE_NAME" } } { "f:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartus/bin/Technology_Viewer.qrui" "2.825 ns" { clk {} clk~combout {} clk~clkctrl {} ss[0] {} } { 0.000ns 0.000ns 0.139ns 0.920ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "PWM.vhd" "" { Text "D:/程序/PWM/PWM.vhd" 41 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "6.576 ns" { ss[0] Add4~109 Add4~111 Add4~113 Add4~115 Add4~116 LessThan1~406 clkout~220 clkout } "NODE_NAME" } } { "f:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartus/bin/Technology_Viewer.qrui" "6.576 ns" { ss[0] {} Add4~109 {} Add4~111 {} Add4~113 {} Add4~115 {} Add4~116 {} LessThan1~406 {} clkout~220 {} clkout {} } { 0.000ns 1.887ns 0.000ns 0.000ns 0.000ns 0.000ns 1.134ns 0.710ns 0.000ns } { 0.000ns 0.706ns 0.086ns 0.086ns 0.086ns 0.506ns 0.651ns 0.616ns 0.108ns } "" } } { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "3.729 ns" { clk clkout } "NODE_NAME" } } { "f:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartus/bin/Technology_Viewer.qrui" "3.729 ns" { clk {} clk~combout {} clkout {} } { 0.000ns 0.000ns 1.963ns } { 0.000ns 1.100ns 0.666ns } "" } } { "f:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/bin/TimingClosureFloorplan.fld" "" "2.825 ns" { clk clk~clkctrl ss[0] } "NODE_NAME" } } { "f:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/quartus/bin/Technology_Viewer.qrui" "2.825 ns" { clk {} clk~combout {} clk~clkctrl {} ss[0] {} } { 0.000ns 0.000ns 0.139ns 0.920ns } { 0.000ns 1.100ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 7 " "Warning: Circuit may not operate. Detected 7 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0 0}