📄 pwm.cmp
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-- Copyright (C) 1991-2008 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008)
-- Created on Sun May 24 09:23:38 2009
COMPONENT PWM
PORT
(
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
conv : IN STD_LOGIC;
add : IN STD_LOGIC;
sub : IN STD_LOGIC;
bout : OUT STD_LOGIC
);
END COMPONENT;
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