door_control.tan.qmsg

自动门控制程序 VERILOG编写！！！

{ "Info" "ITDB_TH_RESULT" "CNT\[0\] Reset Clock_1Hz -0.800 ns register " "Info: th for register \"CNT\[0\]\" (data pin = \"Reset\", clock pin = \"Clock_1Hz\") is -0.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock_1Hz destination 2.200 ns + Longest register " "Info: + Longest clock path from clock \"Clock_1Hz\" to destination register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 1.800 ns Clock_1Hz 1 CLK PIN_83 3 " "Info: 1: + IC(0.000 ns) + CELL(1.800 ns) = 1.800 ns; Loc. = PIN_83; Fanout = 3; CLK Node = 'Clock_1Hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "" { Clock_1Hz } "NODE_NAME" } "" } } { "Door_Control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/Door_Control.v" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 2.200 ns CNT\[0\] 2 REG LC2 11 " "Info: 2: + IC(0.000 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC2; Fanout = 11; REG Node = 'CNT\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "0.400 ns" { Clock_1Hz CNT[0] } "NODE_NAME" } "" } } { "Door_Control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/Door_Control.v" 31 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 100.00 % " "Info: Total cell delay = 2.200 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "2.200 ns" { Clock_1Hz CNT[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Clock_1Hz Clock_1Hz~out CNT[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.600 ns + " "Info: + Micro hold delay of destination is 1.600 ns" {  } { { "Door_Control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/Door_Control.v" 31 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.600 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns Reset 1 PIN PIN_51 15 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_51; Fanout = 15; PIN Node = 'Reset'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "" { Reset } "NODE_NAME" } "" } } { "Door_Control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/Door_Control.v" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(2.800 ns) 4.600 ns CNT\[0\] 2 REG LC2 11 " "Info: 2: + IC(1.600 ns) + CELL(2.800 ns) = 4.600 ns; Loc. = LC2; Fanout = 11; REG Node = 'CNT\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "4.400 ns" { Reset CNT[0] } "NODE_NAME" } "" } } { "Door_Control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/Door_Control.v" 31 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 65.22 % " "Info: Total cell delay = 3.000 ns ( 65.22 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns 34.78 % " "Info: Total interconnect delay = 1.600 ns ( 34.78 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "4.600 ns" { Reset CNT[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.600 ns" { Reset Reset~out CNT[0] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 0.200ns 2.800ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "2.200 ns" { Clock_1Hz CNT[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Clock_1Hz Clock_1Hz~out CNT[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } } } { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "4.600 ns" { Reset CNT[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.600 ns" { Reset Reset~out CNT[0] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 0.200ns 2.800ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 07 14:15:11 2006 " "Info: Processing ended: Mon Aug 07 14:15:11 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}