📄 door_control.tan.qmsg
字号:
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "Clock_1Hz " "Info: Assuming node \"Clock_1Hz\" is an undefined clock" { } { { "Door_Control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/Door_Control.v" 13 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "Clock_1Hz" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Clock_1Hz register CNT\[0\] register CNT\[2\] 149.25 MHz 6.7 ns Internal " "Info: Clock \"Clock_1Hz\" has Internal fmax of 149.25 MHz between source register \"CNT\[0\]\" and destination register \"CNT\[2\]\" (period= 6.7 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.400 ns + Longest register register " "Info: + Longest register to register delay is 4.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CNT\[0\] 1 REG LC2 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 11; REG Node = 'CNT\[0\]'" { } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "" { CNT[0] } "NODE_NAME" } "" } } { "Door_Control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/Door_Control.v" 31 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(2.800 ns) 4.400 ns CNT\[2\] 2 REG LC4 4 " "Info: 2: + IC(1.600 ns) + CELL(2.800 ns) = 4.400 ns; Loc. = LC4; Fanout = 4; REG Node = 'CNT\[2\]'" { } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "4.400 ns" { CNT[0] CNT[2] } "NODE_NAME" } "" } } { "Door_Control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/Door_Control.v" 31 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 63.64 % " "Info: Total cell delay = 2.800 ns ( 63.64 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns 36.36 % " "Info: Total interconnect delay = 1.600 ns ( 36.36 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "4.400 ns" { CNT[0] CNT[2] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.400 ns" { CNT[0] CNT[2] } { 0.000ns 1.600ns } { 0.000ns 2.800ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock_1Hz destination 2.200 ns + Shortest register " "Info: + Shortest clock path from clock \"Clock_1Hz\" to destination register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 1.800 ns Clock_1Hz 1 CLK PIN_83 3 " "Info: 1: + IC(0.000 ns) + CELL(1.800 ns) = 1.800 ns; Loc. = PIN_83; Fanout = 3; CLK Node = 'Clock_1Hz'" { } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "" { Clock_1Hz } "NODE_NAME" } "" } } { "Door_Control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/Door_Control.v" 13 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 2.200 ns CNT\[2\] 2 REG LC4 4 " "Info: 2: + IC(0.000 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC4; Fanout = 4; REG Node = 'CNT\[2\]'" { } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "0.400 ns" { Clock_1Hz CNT[2] } "NODE_NAME" } "" } } { "Door_Control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/Door_Control.v" 31 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 100.00 % " "Info: Total cell delay = 2.200 ns ( 100.00 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "2.200 ns" { Clock_1Hz CNT[2] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Clock_1Hz Clock_1Hz~out CNT[2] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock_1Hz source 2.200 ns - Longest register " "Info: - Longest clock path from clock \"Clock_1Hz\" to source register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 1.800 ns Clock_1Hz 1 CLK PIN_83 3 " "Info: 1: + IC(0.000 ns) + CELL(1.800 ns) = 1.800 ns; Loc. = PIN_83; Fanout = 3; CLK Node = 'Clock_1Hz'" { } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "" { Clock_1Hz } "NODE_NAME" } "" } } { "Door_Control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/Door_Control.v" 13 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 2.200 ns CNT\[0\] 2 REG LC2 11 " "Info: 2: + IC(0.000 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC2; Fanout = 11; REG Node = 'CNT\[0\]'" { } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "0.400 ns" { Clock_1Hz CNT[0] } "NODE_NAME" } "" } } { "Door_Control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/Door_Control.v" 31 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 100.00 % " "Info: Total cell delay = 2.200 ns ( 100.00 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "2.200 ns" { Clock_1Hz CNT[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Clock_1Hz Clock_1Hz~out CNT[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } } } } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "2.200 ns" { Clock_1Hz CNT[2] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Clock_1Hz Clock_1Hz~out CNT[2] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } } } { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "2.200 ns" { Clock_1Hz CNT[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Clock_1Hz Clock_1Hz~out CNT[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" { } { { "Door_Control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/Door_Control.v" 31 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.000 ns + " "Info: + Micro setup delay of destination is 1.000 ns" { } { { "Door_Control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/Door_Control.v" 31 -1 0 } } } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "4.400 ns" { CNT[0] CNT[2] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.400 ns" { CNT[0] CNT[2] } { 0.000ns 1.600ns } { 0.000ns 2.800ns } } } { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "2.200 ns" { Clock_1Hz CNT[2] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Clock_1Hz Clock_1Hz~out CNT[2] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } } } { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "2.200 ns" { Clock_1Hz CNT[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Clock_1Hz Clock_1Hz~out CNT[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } } } } 0}
{ "Info" "ITDB_TSU_RESULT" "CNT\[0\] Reset Clock_1Hz 3.400 ns register " "Info: tsu for register \"CNT\[0\]\" (data pin = \"Reset\", clock pin = \"Clock_1Hz\") is 3.400 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.600 ns + Longest pin register " "Info: + Longest pin to register delay is 4.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns Reset 1 PIN PIN_51 15 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_51; Fanout = 15; PIN Node = 'Reset'" { } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "" { Reset } "NODE_NAME" } "" } } { "Door_Control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/Door_Control.v" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(2.800 ns) 4.600 ns CNT\[0\] 2 REG LC2 11 " "Info: 2: + IC(1.600 ns) + CELL(2.800 ns) = 4.600 ns; Loc. = LC2; Fanout = 11; REG Node = 'CNT\[0\]'" { } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "4.400 ns" { Reset CNT[0] } "NODE_NAME" } "" } } { "Door_Control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/Door_Control.v" 31 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 65.22 % " "Info: Total cell delay = 3.000 ns ( 65.22 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns 34.78 % " "Info: Total interconnect delay = 1.600 ns ( 34.78 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "4.600 ns" { Reset CNT[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.600 ns" { Reset Reset~out CNT[0] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 0.200ns 2.800ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.000 ns + " "Info: + Micro setup delay of destination is 1.000 ns" { } { { "Door_Control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/Door_Control.v" 31 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock_1Hz destination 2.200 ns - Shortest register " "Info: - Shortest clock path from clock \"Clock_1Hz\" to destination register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 1.800 ns Clock_1Hz 1 CLK PIN_83 3 " "Info: 1: + IC(0.000 ns) + CELL(1.800 ns) = 1.800 ns; Loc. = PIN_83; Fanout = 3; CLK Node = 'Clock_1Hz'" { } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "" { Clock_1Hz } "NODE_NAME" } "" } } { "Door_Control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/Door_Control.v" 13 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 2.200 ns CNT\[0\] 2 REG LC2 11 " "Info: 2: + IC(0.000 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC2; Fanout = 11; REG Node = 'CNT\[0\]'" { } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "0.400 ns" { Clock_1Hz CNT[0] } "NODE_NAME" } "" } } { "Door_Control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/Door_Control.v" 31 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 100.00 % " "Info: Total cell delay = 2.200 ns ( 100.00 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "2.200 ns" { Clock_1Hz CNT[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Clock_1Hz Clock_1Hz~out CNT[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } } } } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "4.600 ns" { Reset CNT[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.600 ns" { Reset Reset~out CNT[0] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 0.200ns 2.800ns } } } { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "2.200 ns" { Clock_1Hz CNT[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Clock_1Hz Clock_1Hz~out CNT[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "Clock_1Hz Door_on_off CNT\[0\] 9.300 ns register " "Info: tco from clock \"Clock_1Hz\" to destination pin \"Door_on_off\" through register \"CNT\[0\]\" is 9.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock_1Hz source 2.200 ns + Longest register " "Info: + Longest clock path from clock \"Clock_1Hz\" to source register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 1.800 ns Clock_1Hz 1 CLK PIN_83 3 " "Info: 1: + IC(0.000 ns) + CELL(1.800 ns) = 1.800 ns; Loc. = PIN_83; Fanout = 3; CLK Node = 'Clock_1Hz'" { } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "" { Clock_1Hz } "NODE_NAME" } "" } } { "Door_Control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/Door_Control.v" 13 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 2.200 ns CNT\[0\] 2 REG LC2 11 " "Info: 2: + IC(0.000 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC2; Fanout = 11; REG Node = 'CNT\[0\]'" { } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "0.400 ns" { Clock_1Hz CNT[0] } "NODE_NAME" } "" } } { "Door_Control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/Door_Control.v" 31 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 100.00 % " "Info: Total cell delay = 2.200 ns ( 100.00 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "2.200 ns" { Clock_1Hz CNT[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Clock_1Hz Clock_1Hz~out CNT[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" { } { { "Door_Control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/Door_Control.v" 31 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.800 ns + Longest register pin " "Info: + Longest register to pin delay is 5.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CNT\[0\] 1 REG LC2 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 11; REG Node = 'CNT\[0\]'" { } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "" { CNT[0] } "NODE_NAME" } "" } } { "Door_Control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/Door_Control.v" 31 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(3.800 ns) 5.400 ns Door_on_off~45 2 COMB LC1 1 " "Info: 2: + IC(1.600 ns) + CELL(3.800 ns) = 5.400 ns; Loc. = LC1; Fanout = 1; COMB Node = 'Door_on_off~45'" { } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "5.400 ns" { CNT[0] Door_on_off~45 } "NODE_NAME" } "" } } { "Door_Control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/Door_Control.v" 18 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 5.800 ns Door_on_off 3 PIN PIN_11 0 " "Info: 3: + IC(0.000 ns) + CELL(0.400 ns) = 5.800 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'Door_on_off'" { } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "0.400 ns" { Door_on_off~45 Door_on_off } "NODE_NAME" } "" } } { "Door_Control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/Door_Control.v" 18 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.200 ns 72.41 % " "Info: Total cell delay = 4.200 ns ( 72.41 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns 27.59 % " "Info: Total interconnect delay = 1.600 ns ( 27.59 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "5.800 ns" { CNT[0] Door_on_off~45 Door_on_off } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.800 ns" { CNT[0] Door_on_off~45 Door_on_off } { 0.000ns 1.600ns 0.000ns } { 0.000ns 3.800ns 0.400ns } } } } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "2.200 ns" { Clock_1Hz CNT[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Clock_1Hz Clock_1Hz~out CNT[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } } } { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "5.800 ns" { CNT[0] Door_on_off~45 Door_on_off } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.800 ns" { CNT[0] Door_on_off~45 Door_on_off } { 0.000ns 1.600ns 0.000ns } { 0.000ns 3.800ns 0.400ns } } } } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "Floor_Arrive Door_on_off 6.000 ns Longest " "Info: Longest tpd from source pin \"Floor_Arrive\" to destination pin \"Door_on_off\" is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns Floor_Arrive 1 PIN PIN_58 5 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_58; Fanout = 5; PIN Node = 'Floor_Arrive'" { } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "" { Floor_Arrive } "NODE_NAME" } "" } } { "Door_Control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/Door_Control.v" 14 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(3.800 ns) 5.600 ns Door_on_off~45 2 COMB LC1 1 " "Info: 2: + IC(1.600 ns) + CELL(3.800 ns) = 5.600 ns; Loc. = LC1; Fanout = 1; COMB Node = 'Door_on_off~45'" { } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "5.400 ns" { Floor_Arrive Door_on_off~45 } "NODE_NAME" } "" } } { "Door_Control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/Door_Control.v" 18 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 6.000 ns Door_on_off 3 PIN PIN_11 0 " "Info: 3: + IC(0.000 ns) + CELL(0.400 ns) = 6.000 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'Door_on_off'" { } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "0.400 ns" { Door_on_off~45 Door_on_off } "NODE_NAME" } "" } } { "Door_Control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/Door_Control.v" 18 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.400 ns 73.33 % " "Info: Total cell delay = 4.400 ns ( 73.33 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns 26.67 % " "Info: Total interconnect delay = 1.600 ns ( 26.67 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control_cmp.qrpt" Compiler "Door_Control" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/db/Door_Control.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/lift_control/Master_Control/Door_Control/" "" "6.000 ns" { Floor_Arrive Door_on_off~45 Door_on_off } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.000 ns" { Floor_Arrive Floor_Arrive~out Door_on_off~45 Door_on_off } { 0.000ns 0.000ns 1.600ns 0.000ns } { 0.000ns 0.200ns 3.800ns 0.400ns } } } } 0}
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