door_control.tan.rpt

自动门控制程序 VERILOG编写！！！

; N/A   ; None         ; 3.400 ns   ; Floor_Arrive         ; CNT[1] ; Clock_1Hz ;
; N/A   ; None         ; 3.400 ns   ; Floor_Arrive         ; CNT[2] ; Clock_1Hz ;
+-------+--------------+------------+----------------------+--------+-----------+


+-----------------------------------------------------------------------+
; tco                                                                   ;
+-------+--------------+------------+--------+-------------+------------+
; Slack ; Required tco ; Actual tco ; From   ; To          ; From Clock ;
+-------+--------------+------------+--------+-------------+------------+
; N/A   ; None         ; 9.300 ns   ; CNT[0] ; Door_on_off ; Clock_1Hz  ;
; N/A   ; None         ; 9.300 ns   ; CNT[1] ; Door_on_off ; Clock_1Hz  ;
; N/A   ; None         ; 9.300 ns   ; CNT[2] ; Door_on_off ; Clock_1Hz  ;
+-------+--------------+------------+--------+-------------+------------+


+----------------------------------------------------------------------------------+
; tpd                                                                              ;
+-------+-------------------+-----------------+----------------------+-------------+
; Slack ; Required P2P Time ; Actual P2P Time ; From                 ; To          ;
+-------+-------------------+-----------------+----------------------+-------------+
; N/A   ; None              ; 6.000 ns        ; Floor_Arrive         ; Door_on_off ;
; N/A   ; None              ; 6.000 ns        ; Slave_Request_Arrive ; Door_on_off ;
; N/A   ; None              ; 6.000 ns        ; En                   ; Door_on_off ;
; N/A   ; None              ; 6.000 ns        ; Reset                ; Door_on_off ;
; N/A   ; None              ; 6.000 ns        ; Delay_Request        ; Door_on_off ;
; N/A   ; None              ; 6.000 ns        ; Ahead_Request        ; Door_on_off ;
+-------+-------------------+-----------------+----------------------+-------------+


+-------------------------------------------------------------------------------------+
; th                                                                                  ;
+---------------+-------------+-----------+----------------------+--------+-----------+
; Minimum Slack ; Required th ; Actual th ; From                 ; To     ; To Clock  ;
+---------------+-------------+-----------+----------------------+--------+-----------+
; N/A           ; None        ; -0.800 ns ; Reset                ; CNT[0] ; Clock_1Hz ;
; N/A           ; None        ; -0.800 ns ; Reset                ; CNT[1] ; Clock_1Hz ;
; N/A           ; None        ; -0.800 ns ; Reset                ; CNT[2] ; Clock_1Hz ;
; N/A           ; None        ; -0.800 ns ; En                   ; CNT[0] ; Clock_1Hz ;
; N/A           ; None        ; -0.800 ns ; En                   ; CNT[1] ; Clock_1Hz ;
; N/A           ; None        ; -0.800 ns ; En                   ; CNT[2] ; Clock_1Hz ;
; N/A           ; None        ; -0.800 ns ; Slave_Request_Arrive ; CNT[0] ; Clock_1Hz ;
; N/A           ; None        ; -0.800 ns ; Slave_Request_Arrive ; CNT[1] ; Clock_1Hz ;
; N/A           ; None        ; -0.800 ns ; Slave_Request_Arrive ; CNT[2] ; Clock_1Hz ;
; N/A           ; None        ; -0.800 ns ; Floor_Arrive         ; CNT[0] ; Clock_1Hz ;
; N/A           ; None        ; -0.800 ns ; Floor_Arrive         ; CNT[1] ; Clock_1Hz ;
; N/A           ; None        ; -0.800 ns ; Floor_Arrive         ; CNT[2] ; Clock_1Hz ;
+---------------+-------------+-----------+----------------------+--------+-----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Mon Aug 07 14:15:10 2006
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off Door_Control -c Door_Control
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "Clock_1Hz" is an undefined clock
Info: Clock "Clock_1Hz" has Internal fmax of 149.25 MHz between source register "CNT[0]" and destination register "CNT[2]" (period= 6.7 ns)
    Info: + Longest register to register delay is 4.400 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 11; REG Node = 'CNT[0]'
        Info: 2: + IC(1.600 ns) + CELL(2.800 ns) = 4.400 ns; Loc. = LC4; Fanout = 4; REG Node = 'CNT[2]'
        Info: Total cell delay = 2.800 ns ( 63.64 % )
        Info: Total interconnect delay = 1.600 ns ( 36.36 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "Clock_1Hz" to destination register is 2.200 ns
            Info: 1: + IC(0.000 ns) + CELL(1.800 ns) = 1.800 ns; Loc. = PIN_83; Fanout = 3; CLK Node = 'Clock_1Hz'
            Info: 2: + IC(0.000 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC4; Fanout = 4; REG Node = 'CNT[2]'
            Info: Total cell delay = 2.200 ns ( 100.00 % )
        Info: - Longest clock path from clock "Clock_1Hz" to source register is 2.200 ns
            Info: 1: + IC(0.000 ns) + CELL(1.800 ns) = 1.800 ns; Loc. = PIN_83; Fanout = 3; CLK Node = 'Clock_1Hz'
            Info: 2: + IC(0.000 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC2; Fanout = 11; REG Node = 'CNT[0]'
            Info: Total cell delay = 2.200 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.300 ns
    Info: + Micro setup delay of destination is 1.000 ns
Info: tsu for register "CNT[0]" (data pin = "Reset", clock pin = "Clock_1Hz") is 3.400 ns
    Info: + Longest pin to register delay is 4.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_51; Fanout = 15; PIN Node = 'Reset'
        Info: 2: + IC(1.600 ns) + CELL(2.800 ns) = 4.600 ns; Loc. = LC2; Fanout = 11; REG Node = 'CNT[0]'
        Info: Total cell delay = 3.000 ns ( 65.22 % )
        Info: Total interconnect delay = 1.600 ns ( 34.78 % )
    Info: + Micro setup delay of destination is 1.000 ns
    Info: - Shortest clock path from clock "Clock_1Hz" to destination register is 2.200 ns
        Info: 1: + IC(0.000 ns) + CELL(1.800 ns) = 1.800 ns; Loc. = PIN_83; Fanout = 3; CLK Node = 'Clock_1Hz'
        Info: 2: + IC(0.000 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC2; Fanout = 11; REG Node = 'CNT[0]'
        Info: Total cell delay = 2.200 ns ( 100.00 % )
Info: tco from clock "Clock_1Hz" to destination pin "Door_on_off" through register "CNT[0]" is 9.300 ns
    Info: + Longest clock path from clock "Clock_1Hz" to source register is 2.200 ns
        Info: 1: + IC(0.000 ns) + CELL(1.800 ns) = 1.800 ns; Loc. = PIN_83; Fanout = 3; CLK Node = 'Clock_1Hz'
        Info: 2: + IC(0.000 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC2; Fanout = 11; REG Node = 'CNT[0]'
        Info: Total cell delay = 2.200 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.300 ns
    Info: + Longest register to pin delay is 5.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 11; REG Node = 'CNT[0]'
        Info: 2: + IC(1.600 ns) + CELL(3.800 ns) = 5.400 ns; Loc. = LC1; Fanout = 1; COMB Node = 'Door_on_off~45'
        Info: 3: + IC(0.000 ns) + CELL(0.400 ns) = 5.800 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'Door_on_off'
        Info: Total cell delay = 4.200 ns ( 72.41 % )
        Info: Total interconnect delay = 1.600 ns ( 27.59 % )
Info: Longest tpd from source pin "Floor_Arrive" to destination pin "Door_on_off" is 6.000 ns
    Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_58; Fanout = 5; PIN Node = 'Floor_Arrive'
    Info: 2: + IC(1.600 ns) + CELL(3.800 ns) = 5.600 ns; Loc. = LC1; Fanout = 1; COMB Node = 'Door_on_off~45'
    Info: 3: + IC(0.000 ns) + CELL(0.400 ns) = 6.000 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'Door_on_off'
    Info: Total cell delay = 4.400 ns ( 73.33 % )
    Info: Total interconnect delay = 1.600 ns ( 26.67 % )
Info: th for register "CNT[0]" (data pin = "Reset", clock pin = "Clock_1Hz") is -0.800 ns
    Info: + Longest clock path from clock "Clock_1Hz" to destination register is 2.200 ns
        Info: 1: + IC(0.000 ns) + CELL(1.800 ns) = 1.800 ns; Loc. = PIN_83; Fanout = 3; CLK Node = 'Clock_1Hz'
        Info: 2: + IC(0.000 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC2; Fanout = 11; REG Node = 'CNT[0]'
        Info: Total cell delay = 2.200 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 1.600 ns
    Info: - Shortest pin to register delay is 4.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_51; Fanout = 15; PIN Node = 'Reset'
        Info: 2: + IC(1.600 ns) + CELL(2.800 ns) = 4.600 ns; Loc. = LC2; Fanout = 11; REG Node = 'CNT[0]'
        Info: Total cell delay = 3.000 ns ( 65.22 % )
        Info: Total interconnect delay = 1.600 ns ( 34.78 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Mon Aug 07 14:15:11 2006
    Info: Elapsed time: 00:00:02