frequency.tan.rpt

该程序是基于FPGA的硬件描述语言

+-------+--------------+------------+----------+----+------------+
; Slack ; Required tco ; Actual tco ; From     ; To ; From Clock ;
+-------+--------------+------------+----------+----+------------+
; N/A   ; None         ; 8.601 ns   ; \flag2:t ; q  ; clk        ;
+-------+--------------+------------+----------+----+------------+


+---------------------------------------------------------------------------+
; th                                                                        ;
+---------------+-------------+-----------+--------+-------------+----------+
; Minimum Slack ; Required th ; Actual th ; From   ; To          ; To Clock ;
+---------------+-------------+-----------+--------+-------------+----------+
; N/A           ; None        ; -3.597 ns ; ain[6] ; \flag1:Q[6] ; clk      ;
; N/A           ; None        ; -3.598 ns ; ain[5] ; \flag1:Q[5] ; clk      ;
; N/A           ; None        ; -3.619 ns ; ain[7] ; \flag1:Q[7] ; clk      ;
; N/A           ; None        ; -4.005 ns ; ain[2] ; \flag1:Q[2] ; clk      ;
; N/A           ; None        ; -4.009 ns ; ain[0] ; \flag1:Q[0] ; clk      ;
; N/A           ; None        ; -4.025 ns ; ain[3] ; \flag1:Q[3] ; clk      ;
; N/A           ; None        ; -4.037 ns ; ain[4] ; \flag1:Q[4] ; clk      ;
; N/A           ; None        ; -4.045 ns ; ain[1] ; \flag1:Q[1] ; clk      ;
; N/A           ; None        ; -4.730 ns ; ain[8] ; \flag1:Q[8] ; clk      ;
+---------------+-------------+-----------+--------+-------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Sun May 17 16:02:43 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off frequency -c frequency --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "f" as buffer
Info: Clock "clk" has Internal fmax of 195.73 MHz between source register "\flag1:Q[7]" and destination register "\flag1:Q[8]" (period= 5.109 ns)
    Info: + Longest register to register delay is 4.848 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y17_N7; Fanout = 4; REG Node = '\flag1:Q[7]'
        Info: 2: + IC(1.254 ns) + CELL(0.590 ns) = 1.844 ns; Loc. = LC_X2_Y18_N2; Fanout = 2; COMB Node = 'Equal0~83'
        Info: 3: + IC(1.198 ns) + CELL(0.114 ns) = 3.156 ns; Loc. = LC_X2_Y17_N9; Fanout = 9; COMB Node = 'Equal0~84'
        Info: 4: + IC(0.467 ns) + CELL(1.225 ns) = 4.848 ns; Loc. = LC_X2_Y17_N8; Fanout = 3; REG Node = '\flag1:Q[8]'
        Info: Total cell delay = 1.929 ns ( 39.79 % )
        Info: Total interconnect delay = 2.919 ns ( 60.21 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.954 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 10; CLK Node = 'clk'
            Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X2_Y17_N8; Fanout = 3; REG Node = '\flag1:Q[8]'
            Info: Total cell delay = 2.180 ns ( 73.80 % )
            Info: Total interconnect delay = 0.774 ns ( 26.20 % )
        Info: - Longest clock path from clock "clk" to source register is 2.954 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 10; CLK Node = 'clk'
            Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X2_Y17_N7; Fanout = 4; REG Node = '\flag1:Q[7]'
            Info: Total cell delay = 2.180 ns ( 73.80 % )
            Info: Total interconnect delay = 0.774 ns ( 26.20 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "\flag1:Q[8]" (data pin = "ain[8]", clock pin = "clk") is 4.782 ns
    Info: + Longest pin to register delay is 7.699 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_39; Fanout = 1; PIN Node = 'ain[8]'
        Info: 2: + IC(6.115 ns) + CELL(0.115 ns) = 7.699 ns; Loc. = LC_X2_Y17_N8; Fanout = 3; REG Node = '\flag1:Q[8]'
        Info: Total cell delay = 1.584 ns ( 20.57 % )
        Info: Total interconnect delay = 6.115 ns ( 79.43 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.954 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 10; CLK Node = 'clk'
        Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X2_Y17_N8; Fanout = 3; REG Node = '\flag1:Q[8]'
        Info: Total cell delay = 2.180 ns ( 73.80 % )
        Info: Total interconnect delay = 0.774 ns ( 26.20 % )
Info: tco from clock "clk" to destination pin "q" through register "\flag2:t" is 8.601 ns
    Info: + Longest clock path from clock "clk" to source register is 4.664 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 10; CLK Node = 'clk'
        Info: 2: + IC(0.774 ns) + CELL(0.935 ns) = 3.178 ns; Loc. = LC_X2_Y17_N9; Fanout = 1; REG Node = 'f'
        Info: 3: + IC(0.775 ns) + CELL(0.711 ns) = 4.664 ns; Loc. = LC_X1_Y17_N2; Fanout = 2; REG Node = '\flag2:t'
        Info: Total cell delay = 3.115 ns ( 66.79 % )
        Info: Total interconnect delay = 1.549 ns ( 33.21 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 3.713 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y17_N2; Fanout = 2; REG Node = '\flag2:t'
        Info: 2: + IC(1.589 ns) + CELL(2.124 ns) = 3.713 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'q'
        Info: Total cell delay = 2.124 ns ( 57.20 % )
        Info: Total interconnect delay = 1.589 ns ( 42.80 % )
Info: th for register "\flag1:Q[6]" (data pin = "ain[6]", clock pin = "clk") is -3.597 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.954 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 10; CLK Node = 'clk'
        Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X2_Y17_N6; Fanout = 4; REG Node = '\flag1:Q[6]'
        Info: Total cell delay = 2.180 ns ( 73.80 % )
        Info: Total interconnect delay = 0.774 ns ( 26.20 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 6.566 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_12; Fanout = 1; PIN Node = 'ain[6]'
        Info: 2: + IC(4.982 ns) + CELL(0.115 ns) = 6.566 ns; Loc. = LC_X2_Y17_N6; Fanout = 4; REG Node = '\flag1:Q[6]'
        Info: Total cell delay = 1.584 ns ( 24.12 % )
        Info: Total interconnect delay = 4.982 ns ( 75.88 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Allocated 106 megabytes of memory during processing
    Info: Processing ended: Sun May 17 16:02:44 2009
    Info: Elapsed time: 00:00:01