system.h

用Quartus II 8.0（32bit）

/* system.h
 *
 * Machine generated for a CPU named "cpu" as defined in:
 * e:\EDA\NIOS_TFT\software\tft_syslib\..\..\nios_lcd.ptf
 *
 * Generated: 2009-04-25 11:21:27.484
 *
 */

#ifndef __SYSTEM_H_
#define __SYSTEM_H_

/*

DO NOT MODIFY THIS FILE

   Changing this file will have subtle consequences
   which will almost certainly lead to a nonfunctioning
   system. If you do modify this file, be aware that your
   changes will be overwritten and lost when this file
   is generated again.

DO NOT MODIFY THIS FILE

*/

/******************************************************************************
*                                                                             *
* License Agreement                                                           *
*                                                                             *
* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
* All rights reserved.                                                        *
*                                                                             *
* Permission is hereby granted, free of charge, to any person obtaining a     *
* copy of this software and associated documentation files (the "Software"),  *
* to deal in the Software without restriction, including without limitation   *
* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
* and/or sell copies of the Software, and to permit persons to whom the       *
* Software is furnished to do so, subject to the following conditions:        *
*                                                                             *
* The above copyright notice and this permission notice shall be included in  *
* all copies or substantial portions of the Software.                         *
*                                                                             *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
* DEALINGS IN THE SOFTWARE.                                                   *
*                                                                             *
* This agreement shall be governed in all respects by the laws of the State   *
* of California and by the laws of the United States of America.              *
*                                                                             *
******************************************************************************/

/*
 * system configuration
 *
 */

#define ALT_SYSTEM_NAME "nios_lcd"
#define ALT_CPU_NAME "cpu"
#define ALT_CPU_ARCHITECTURE "altera_nios2"
#define ALT_DEVICE_FAMILY "CYCLONEII"
#define ALT_STDIN "/dev/jtag_uart"
#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
#define ALT_STDIN_BASE 0x010020c0
#define ALT_STDIN_DEV jtag_uart
#define ALT_STDIN_PRESENT
#define ALT_STDOUT "/dev/jtag_uart"
#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart"
#define ALT_STDOUT_BASE 0x010020c0
#define ALT_STDOUT_DEV jtag_uart
#define ALT_STDOUT_PRESENT
#define ALT_STDERR "/dev/jtag_uart"
#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
#define ALT_STDERR_BASE 0x010020c0
#define ALT_STDERR_DEV jtag_uart
#define ALT_STDERR_PRESENT
#define ALT_CPU_FREQ 50000000
#define ALT_IRQ_BASE NULL

/*
 * processor configuration
 *
 */

#define NIOS2_CPU_IMPLEMENTATION "fast"
#define NIOS2_BIG_ENDIAN 0

#define NIOS2_ICACHE_SIZE 4096
#define NIOS2_DCACHE_SIZE 2048
#define NIOS2_ICACHE_LINE_SIZE 32
#define NIOS2_ICACHE_LINE_SIZE_LOG2 5
#define NIOS2_DCACHE_LINE_SIZE 32
#define NIOS2_DCACHE_LINE_SIZE_LOG2 5
#define NIOS2_FLUSHDA_SUPPORTED

#define NIOS2_EXCEPTION_ADDR 0x00800020
#define NIOS2_RESET_ADDR 0x01001800
#define NIOS2_BREAK_ADDR 0x01001020

#define NIOS2_HAS_DEBUG_STUB

#define NIOS2_CPU_ID_SIZE 1
#define NIOS2_CPU_ID_VALUE 0

/*
 * A define for each class of peripheral
 *
 */

#define __ALTERA_AVALON_JTAG_UART
#define __ALTERA_AVALON_EPCS_FLASH_CONTROLLER
#define __ALTERA_AVALON_PIO
#define __ALTERA_AVALON_NEW_SDRAM_CONTROLLER

/*
 * jtag_uart configuration
 *
 */

#define JTAG_UART_NAME "/dev/jtag_uart"
#define JTAG_UART_TYPE "altera_avalon_jtag_uart"
#define JTAG_UART_BASE 0x010020c0
#define JTAG_UART_SPAN 8
#define JTAG_UART_IRQ 0
#define JTAG_UART_WRITE_DEPTH 64
#define JTAG_UART_READ_DEPTH 64
#define JTAG_UART_WRITE_THRESHOLD 8
#define JTAG_UART_READ_THRESHOLD 8
#define JTAG_UART_READ_CHAR_STREAM ""
#define JTAG_UART_SHOWASCII 1
#define JTAG_UART_READ_LE 0
#define JTAG_UART_WRITE_LE 0
#define JTAG_UART_ALTERA_SHOW_UNRELEASED_JTAG_UART_FEATURES 0
#define ALT_MODULE_CLASS_jtag_uart altera_avalon_jtag_uart

/*
 * epcs_controller configuration
 *
 */

#define EPCS_CONTROLLER_NAME "/dev/epcs_controller"
#define EPCS_CONTROLLER_TYPE "altera_avalon_epcs_flash_controller"
#define EPCS_CONTROLLER_BASE 0x01001800
#define EPCS_CONTROLLER_SPAN 2048
#define EPCS_CONTROLLER_IRQ 1
#define EPCS_CONTROLLER_DATABITS 8
#define EPCS_CONTROLLER_TARGETCLOCK 20
#define EPCS_CONTROLLER_CLOCKUNITS "MHz"
#define EPCS_CONTROLLER_CLOCKMULT 1000000
#define EPCS_CONTROLLER_NUMSLAVES 1
#define EPCS_CONTROLLER_ISMASTER 1
#define EPCS_CONTROLLER_CLOCKPOLARITY 0
#define EPCS_CONTROLLER_CLOCKPHASE 0
#define EPCS_CONTROLLER_LSBFIRST 0
#define EPCS_CONTROLLER_EXTRADELAY 0
#define EPCS_CONTROLLER_TARGETSSDELAY 100
#define EPCS_CONTROLLER_DELAYUNITS "us"
#define EPCS_CONTROLLER_DELAYMULT "1e-006"
#define EPCS_CONTROLLER_PREFIX "epcs_"
#define EPCS_CONTROLLER_REGISTER_OFFSET 0x200
#define EPCS_CONTROLLER_USE_ASMI_ATOM 1
#define EPCS_CONTROLLER_CLOCKUNIT "kHz"
#define EPCS_CONTROLLER_DELAYUNIT "us"
#define ALT_MODULE_CLASS_epcs_controller altera_avalon_epcs_flash_controller

/*
 * TFT_DATA configuration
 *
 */

#define TFT_DATA_NAME "/dev/TFT_DATA"
#define TFT_DATA_TYPE "altera_avalon_pio"
#define TFT_DATA_BASE 0x01002000
#define TFT_DATA_SPAN 16
#define TFT_DATA_DO_TEST_BENCH_WIRING 0
#define TFT_DATA_DRIVEN_SIM_VALUE 0
#define TFT_DATA_HAS_TRI 0
#define TFT_DATA_HAS_OUT 1
#define TFT_DATA_HAS_IN 0
#define TFT_DATA_CAPTURE 0
#define TFT_DATA_DATA_WIDTH 8
#define TFT_DATA_EDGE_TYPE "NONE"
#define TFT_DATA_IRQ_TYPE "NONE"
#define TFT_DATA_BIT_CLEARING_EDGE_REGISTER 0
#define TFT_DATA_FREQ 50000000
#define ALT_MODULE_CLASS_TFT_DATA altera_avalon_pio

/*
 * RS configuration
 *
 */

#define RS_NAME "/dev/RS"
#define RS_TYPE "altera_avalon_pio"
#define RS_BASE 0x01002010
#define RS_SPAN 16
#define RS_DO_TEST_BENCH_WIRING 0
#define RS_DRIVEN_SIM_VALUE 0
#define RS_HAS_TRI 0
#define RS_HAS_OUT 1
#define RS_HAS_IN 0
#define RS_CAPTURE 0
#define RS_DATA_WIDTH 1
#define RS_EDGE_TYPE "NONE"
#define RS_IRQ_TYPE "NONE"
#define RS_BIT_CLEARING_EDGE_REGISTER 0
#define RS_FREQ 50000000
#define ALT_MODULE_CLASS_RS altera_avalon_pio

/*
 * RW configuration
 *
 */

#define RW_NAME "/dev/RW"
#define RW_TYPE "altera_avalon_pio"
#define RW_BASE 0x01002020
#define RW_SPAN 16
#define RW_DO_TEST_BENCH_WIRING 0
#define RW_DRIVEN_SIM_VALUE 0
#define RW_HAS_TRI 0
#define RW_HAS_OUT 1
#define RW_HAS_IN 0
#define RW_CAPTURE 0
#define RW_DATA_WIDTH 1
#define RW_EDGE_TYPE "NONE"
#define RW_IRQ_TYPE "NONE"
#define RW_BIT_CLEARING_EDGE_REGISTER 0
#define RW_FREQ 50000000
#define ALT_MODULE_CLASS_RW altera_avalon_pio

/*
 * RD configuration
 *
 */

#define RD_NAME "/dev/RD"
#define RD_TYPE "altera_avalon_pio"
#define RD_BASE 0x01002030
#define RD_SPAN 16
#define RD_DO_TEST_BENCH_WIRING 0
#define RD_DRIVEN_SIM_VALUE 0
#define RD_HAS_TRI 0
#define RD_HAS_OUT 1
#define RD_HAS_IN 0
#define RD_CAPTURE 0
#define RD_DATA_WIDTH 1
#define RD_EDGE_TYPE "NONE"
#define RD_IRQ_TYPE "NONE"
#define RD_BIT_CLEARING_EDGE_REGISTER 0
#define RD_FREQ 50000000
#define ALT_MODULE_CLASS_RD altera_avalon_pio

/*
 * CS configuration
 *
 */

#define CS_NAME "/dev/CS"
#define CS_TYPE "altera_avalon_pio"
#define CS_BASE 0x01002040
#define CS_SPAN 16
#define CS_DO_TEST_BENCH_WIRING 0
#define CS_DRIVEN_SIM_VALUE 0
#define CS_HAS_TRI 0
#define CS_HAS_OUT 1
#define CS_HAS_IN 0
#define CS_CAPTURE 0
#define CS_DATA_WIDTH 1
#define CS_EDGE_TYPE "NONE"
#define CS_IRQ_TYPE "NONE"
#define CS_BIT_CLEARING_EDGE_REGISTER 0
#define CS_FREQ 50000000
#define ALT_MODULE_CLASS_CS altera_avalon_pio

/*
 * RES configuration
 *
 */

#define RES_NAME "/dev/RES"
#define RES_TYPE "altera_avalon_pio"
#define RES_BASE 0x01002050
#define RES_SPAN 16
#define RES_DO_TEST_BENCH_WIRING 0
#define RES_DRIVEN_SIM_VALUE 0
#define RES_HAS_TRI 0
#define RES_HAS_OUT 1
#define RES_HAS_IN 0
#define RES_CAPTURE 0
#define RES_DATA_WIDTH 1
#define RES_EDGE_TYPE "NONE"
#define RES_IRQ_TYPE "NONE"
#define RES_BIT_CLEARING_EDGE_REGISTER 0
#define RES_FREQ 50000000
#define ALT_MODULE_CLASS_RES altera_avalon_pio

/*
 * sdram configuration
 *
 */

#define SDRAM_NAME "/dev/sdram"
#define SDRAM_TYPE "altera_avalon_new_sdram_controller"
#define SDRAM_BASE 0x00800000
#define SDRAM_SPAN 8388608
#define SDRAM_REGISTER_DATA_IN 1
#define SDRAM_SIM_MODEL_BASE 1
#define SDRAM_SDRAM_DATA_WIDTH 16
#define SDRAM_SDRAM_ADDR_WIDTH 12
#define SDRAM_SDRAM_ROW_WIDTH 12
#define SDRAM_SDRAM_COL_WIDTH 8
#define SDRAM_SDRAM_NUM_CHIPSELECTS 1
#define SDRAM_SDRAM_NUM_BANKS 4
#define SDRAM_REFRESH_PERIOD 15.625
#define SDRAM_POWERUP_DELAY 100.0
#define SDRAM_CAS_LATENCY 3
#define SDRAM_T_RFC 70.0
#define SDRAM_T_RP 20.0
#define SDRAM_T_MRD 3
#define SDRAM_T_RCD 20.0
#define SDRAM_T_AC 5.5
#define SDRAM_T_WR 14.0
#define SDRAM_INIT_REFRESH_COMMANDS 2
#define SDRAM_INIT_NOP_DELAY 0.0
#define SDRAM_SHARED_DATA 0
#define SDRAM_SDRAM_BANK_WIDTH 2
#define SDRAM_TRISTATE_BRIDGE_SLAVE ""
#define SDRAM_STARVATION_INDICATOR 0
#define SDRAM_IS_INITIALIZED 1
#define ALT_MODULE_CLASS_sdram altera_avalon_new_sdram_controller

/*
 * T_DO configuration
 *
 */

#define T_DO_NAME "/dev/T_DO"
#define T_DO_TYPE "altera_avalon_pio"
#define T_DO_BASE 0x01002060
#define T_DO_SPAN 16
#define T_DO_DO_TEST_BENCH_WIRING 0
#define T_DO_DRIVEN_SIM_VALUE 0
#define T_DO_HAS_TRI 0
#define T_DO_HAS_OUT 1
#define T_DO_HAS_IN 0
#define T_DO_CAPTURE 0
#define T_DO_DATA_WIDTH 1
#define T_DO_EDGE_TYPE "NONE"
#define T_DO_IRQ_TYPE "NONE"
#define T_DO_BIT_CLEARING_EDGE_REGISTER 0
#define T_DO_FREQ 50000000
#define ALT_MODULE_CLASS_T_DO altera_avalon_pio

/*
 * T_DIN configuration
 *
 */

#define T_DIN_NAME "/dev/T_DIN"
#define T_DIN_TYPE "altera_avalon_pio"
#define T_DIN_BASE 0x01002070
#define T_DIN_SPAN 16
#define T_DIN_DO_TEST_BENCH_WIRING 0
#define T_DIN_DRIVEN_SIM_VALUE 0
#define T_DIN_HAS_TRI 0
#define T_DIN_HAS_OUT 1
#define T_DIN_HAS_IN 0
#define T_DIN_CAPTURE 0
#define T_DIN_DATA_WIDTH 1
#define T_DIN_EDGE_TYPE "NONE"
#define T_DIN_IRQ_TYPE "NONE"
#define T_DIN_BIT_CLEARING_EDGE_REGISTER 0
#define T_DIN_FREQ 50000000
#define ALT_MODULE_CLASS_T_DIN altera_avalon_pio

/*
 * T_CLK configuration
 *
 */

#define T_CLK_NAME "/dev/T_CLK"
#define T_CLK_TYPE "altera_avalon_pio"
#define T_CLK_BASE 0x01002080
#define T_CLK_SPAN 16
#define T_CLK_DO_TEST_BENCH_WIRING 0
#define T_CLK_DRIVEN_SIM_VALUE 0
#define T_CLK_HAS_TRI 0
#define T_CLK_HAS_OUT 1
#define T_CLK_HAS_IN 0
#define T_CLK_CAPTURE 0
#define T_CLK_DATA_WIDTH 1
#define T_CLK_EDGE_TYPE "NONE"
#define T_CLK_IRQ_TYPE "NONE"
#define T_CLK_BIT_CLEARING_EDGE_REGISTER 0
#define T_CLK_FREQ 50000000
#define ALT_MODULE_CLASS_T_CLK altera_avalon_pio

/*
 * T_CS configuration
 *
 */

#define T_CS_NAME "/dev/T_CS"
#define T_CS_TYPE "altera_avalon_pio"
#define T_CS_BASE 0x01002090
#define T_CS_SPAN 16
#define T_CS_DO_TEST_BENCH_WIRING 0
#define T_CS_DRIVEN_SIM_VALUE 0
#define T_CS_HAS_TRI 0
#define T_CS_HAS_OUT 1
#define T_CS_HAS_IN 0
#define T_CS_CAPTURE 0
#define T_CS_DATA_WIDTH 1
#define T_CS_EDGE_TYPE "NONE"
#define T_CS_IRQ_TYPE "NONE"
#define T_CS_BIT_CLEARING_EDGE_REGISTER 0
#define T_CS_FREQ 50000000
#define ALT_MODULE_CLASS_T_CS altera_avalon_pio

/*
 * INT configuration
 *
 */

#define INT_NAME "/dev/INT"
#define INT_TYPE "altera_avalon_pio"
#define INT_BASE 0x010020a0
#define INT_SPAN 16
#define INT_DO_TEST_BENCH_WIRING 0
#define INT_DRIVEN_SIM_VALUE 0
#define INT_HAS_TRI 0
#define INT_HAS_OUT 1
#define INT_HAS_IN 0
#define INT_CAPTURE 0
#define INT_DATA_WIDTH 1
#define INT_EDGE_TYPE "NONE"
#define INT_IRQ_TYPE "NONE"
#define INT_BIT_CLEARING_EDGE_REGISTER 0
#define INT_FREQ 50000000
#define ALT_MODULE_CLASS_INT altera_avalon_pio

/*
 * T_BUSY configuration
 *
 */

#define T_BUSY_NAME "/dev/T_BUSY"
#define T_BUSY_TYPE "altera_avalon_pio"
#define T_BUSY_BASE 0x010020b0
#define T_BUSY_SPAN 16
#define T_BUSY_DO_TEST_BENCH_WIRING 0
#define T_BUSY_DRIVEN_SIM_VALUE 0
#define T_BUSY_HAS_TRI 0
#define T_BUSY_HAS_OUT 1
#define T_BUSY_HAS_IN 1
#define T_BUSY_CAPTURE 0
#define T_BUSY_DATA_WIDTH 1
#define T_BUSY_EDGE_TYPE "NONE"
#define T_BUSY_IRQ_TYPE "NONE"
#define T_BUSY_BIT_CLEARING_EDGE_REGISTER 0
#define T_BUSY_FREQ 50000000
#define ALT_MODULE_CLASS_T_BUSY altera_avalon_pio

/*
 * system library configuration
 *
 */

#define ALT_MAX_FD 32
#define ALT_SYS_CLK none
#define ALT_TIMESTAMP_CLK none

/*
 * Devices associated with code sections.
 *
 */

#define ALT_TEXT_DEVICE       SDRAM
#define ALT_RODATA_DEVICE     SDRAM
#define ALT_RWDATA_DEVICE     SDRAM
#define ALT_EXCEPTIONS_DEVICE SDRAM
#define ALT_RESET_DEVICE      EPCS_CONTROLLER


#endif /* __SYSTEM_H_ */