i8237a_tb.vhd

经典DMA控制器8237A的VHDL设计

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-- Intel 8237A DMA Controller Testbench
-- Roman Lysecky
-- 07/16/1999
-- Version 1.1(Small)
-- Notes: Testbench for DMA controller. Only tests single transfer and
--        some program operation.

-----------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;

-----------------------------------------------------------------------------

entity I8237A_TB is
end I8237A_TB;

-----------------------------------------------------------------------------

architecture TB of I8237A_TB is

    --
    -- component declarations
    --
    component I8237A
        port(clk   : in    STD_LOGIC;
             cs    : in    STD_LOGIC;
             reset : in    STD_LOGIC;
             ready : in    STD_LOGIC;
             hlda  : in    STD_LOGIC;
             dreq  : in    UNSIGNED(3 downto 0);
             db    : inout UNSIGNED(7 downto 0);
             ior   : inout STD_LOGIC;
             iow   : inout STD_LOGIC;
             eopp  : inout STD_LOGIC;
             a3_0  : inout UNSIGNED(3 downto 0);
             a7_4  : out   UNSIGNED(3 downto 0);
             hrq   : out   STD_LOGIC;
             dack  : out   UNSIGNED(3 downto 0);
             aen   : out   STD_LOGIC;
             adstb : out   STD_LOGIC;
             memr  : out   STD_LOGIC;
             memw  : out   STD_LOGIC);
    end component;

    --
    -- signal declarations
    --
    signal clk   : STD_LOGIC := '0';
    signal cs    : STD_LOGIC;
    signal reset : STD_LOGIC;
    signal ready : STD_LOGIC;
    signal hlda  : STD_LOGIC;
    signal dreq  : UNSIGNED(3 downto 0);
    signal db    : UNSIGNED(7 downto 0);
    signal ior   : STD_LOGIC;
    signal iow   : STD_LOGIC;
    signal eopp  : STD_LOGIC;
    signal a3_0  : UNSIGNED(3 downto 0);
    signal a7_4  : UNSIGNED(3 downto 0);
    signal hrq   : STD_LOGIC;
    signal dack  : UNSIGNED(3 downto 0);
    signal aen   : STD_LOGIC;
    signal adstb : STD_LOGIC;
    signal memr  : STD_LOGIC;
    signal memw  : STD_LOGIC;

begin
    
    --
    -- component instantiations
    --
    I8237A_1 : I8237A port map(clk, cs, reset, ready, hlda, dreq, db,
                               ior, iow, eopp, a3_0,  a7_4, hrq, dack, 
                               aen, adstb, memr, memw );

    --
    -- generate clock
    --
    clk <= not clk after 10 ns;

    --
    -- testbench process
    --
    process
        variable temp : INTEGER;
    begin

        --
        -- initialize values
        --
        cs    <= '1';
        ready <= '0';
        hlda  <= '0';
        dreq  <= "0000";
        db    <= "ZZZZZZZZ";
        ior   <= 'Z';
        iow   <= 'Z';
        eopp  <= 'Z';
        a3_0  <= "ZZZZ";

        --
        -- reset dma controller
        --
        reset <= '1';
        wait for 10 ns;
        reset <= '0';
        wait until clk'event and clk = '1';

        --
        -- program command register
        --
        cs   <= '0';
        ior  <= '1';
        iow  <= '0';
        a3_0 <= "1000";
        db   <= "10000000";
        wait until clk'event and clk = '1';
        wait until clk'event and clk = '1';
        wait until clk'event and clk = '0';

        -- 
        -- verify command register write
        --
        -- 0 => "0000"
        assert( dack = 0 ) REPORT "Failed command program." severity error;

        --
        -- program mode register for channel 0
        --
        ior  <= '1';
        iow  <= '0';
        a3_0 <= "1011";
        db   <= "10010100";
        wait until clk'event and clk = '1';

        --
        -- program base and current word count register for channel 0
        --
        ior  <= '1';
        iow  <= '0';
        a3_0 <= "0001";
        db   <= "00000011";
        wait until clk'event and clk = '1';

        ior  <= '1';
        iow  <= '0';
        a3_0 <= "0001";
        db   <= "00000000";
        wait until clk'event and clk = '1';

        --
        -- verify current word count program
        --
        ior  <= '0';
        iow  <= '1';
        a3_0 <= "0001";
        db   <= "ZZZZZZZZ";
        wait until clk'event and clk = '1';
        wait until clk'event and clk = '0';
        assert( db = 3 ) REPORT "Failed Base and Current Word(7 downto 0) program." severity error;

        ior  <= '0';
        iow  <= '1';
        a3_0 <= "0001";
        db   <= "ZZZZZZZZ";
        wait until clk'event and clk = '1';
        wait until clk'event and clk = '0';
        assert( db = 0 ) REPORT "Failed Base and Current Word(15 downto 8) program." severity error;

	--
	-- request service for channel 0
	--
        dreq(0) <= '1';        
        cs      <= '1';
        ior     <= 'Z';
        iow     <= 'Z';
        a3_0    <= "ZZZZ";
        db      <= "ZZZZZZZZ";
        wait until clk'event and clk = '1';

        --
        -- enable dma
        --
        cs   <= '1';
        ior  <= 'Z';
        iow  <= 'Z';
        a3_0 <= "ZZZZ";
        db   <= "ZZZZZZZZ";
        wait until clk'event and clk = '1';
        wait until clk'event and clk = '0';

        --
        -- verify hrq
        --
        assert( hrq = '1' ) REPORT "Failed in STATE: IDLE." severity error;

        --
        -- relinquish bus to dma controller
        --
        cs   <= '1';
        ior  <= 'Z';
        iow  <= 'Z';
        a3_0 <= "ZZZZ";
        db   <= "ZZZZZZZZ";
        hlda <= '1';
        wait until clk'event and clk = '1';
        wait until clk'event and clk = '1';
        wait until clk'event and clk = '0';

        --
        -- verify state SS1
        --
        assert( aen = '1' )   REPORT "Failed aen STATE: SS1"   severity error;
        assert( adstb = '0' ) REPORT "Failed adstb STATE: SS1" severity error;
        assert( hrq = '1' )   REPORT "Failed hrq STATE: SS1"   severity error;
        assert( dack = 0 )    REPORT "Failed dack STATE: SS1"  severity error;
        wait until clk'event and clk = '1';
        wait until clk'event and clk = '0';

        --
        -- verify state SS2
        --
        assert( aen = '1' )   REPORT "Failed aen STATE: SS2"                 severity error;
        assert( adstb = '1' ) REPORT "Failed adstb STATE: SS2"               severity error;
        assert( hrq = '1' )   REPORT "Failed hrq STATE: SS2"                 severity error;
        assert( dack = 1 )    REPORT "Failed dack STATE: SS2"                severity error;
        assert( a3_0 = 0 )    REPORT "Failed address(3 downto 0) STATE: SS2" severity error;
        assert( a7_4 = 0 )    REPORT "Failed address(7 downto 4) STATE: SS2" severity error;
        assert( db = 0 )      REPORT "Failed db STATE: SS2" severity error;
        wait until clk'event and clk = '1';
        wait until clk'event and clk = '0';

        --
        -- test block transfer operation
        --
        for temp in 0 to 3 loop

            --
            -- verify state SS3
            --
            assert( aen = '1' ) REPORT "Failed aen STATE: SS3"                   severity error;
            assert( adstb = '0' ) REPORT "Failed adstb STATE: SS3"               severity error;
            assert( hrq = '1' ) REPORT "Failed hrq STATE: SS3"                   severity error;
            assert( dack = 1 ) REPORT "Failed dack STATE: SS3"                   severity error;
            assert( a3_0 = temp ) REPORT "Failed address(3 downto 0) STATE: SS3" severity error;
            assert( a7_4 = 0 ) REPORT "Failed address(7 downto 4) STATE: SS3"    severity error;
            wait until clk'event and clk = '1';
            wait until clk'event and clk = '0';

            --
            -- verify state SS4
            --
            assert( aen = '1' )   REPORT "Failed aen STATE: SS4"                 severity error;
            assert( adstb = '0' ) REPORT "Failed adstb STATE: SS4"               severity error;
            assert( hrq = '1' )   REPORT "Failed hrq STATE: SS4"                 severity error;
            assert( dack = 1 )    REPORT "Failed dack STATE: SS4"                severity error;
            assert( a3_0 = temp ) REPORT "Failed address(3 downto 0) STATE: SS4" severity error;
            assert( a7_4 = 0 )    REPORT "Failed address(7 downto 4) STATE: SS4" severity error;
            wait until clk'event and clk = '1';
            wait until clk'event and clk = '0';

            if( temp = 3 ) then
    
                --
                -- verify state IDLE
                --
                assert( aen = '0' )   REPORT "Failed aen STATE: IDLE"   severity error;
                assert( adstb = '0' ) REPORT "Failed adstb STATE: IDLE" severity error;
                assert( hrq = '0' )   REPORT "Failed hrq STATE: IDLE"   severity error;
                assert( dack = 0 )    REPORT "Failed dack STATE: IDLE"  severity error;
            else
                --
                -- verify state SSB2
                --
                assert( aen = '1' )     REPORT "Failed aen STATE: SSB2"                 severity error;
                assert( adstb = '0' )   REPORT "Failed adstb STATE: SSB2"               severity error;
                assert( hrq = '1' )     REPORT "Failed hrq STATE: SSB2"                 severity error;
                assert( dack = 1 )      REPORT "Failed dack STATE: SSB2"                severity error;
                assert( a3_0 = temp+1 ) REPORT "Failed address(3 downto 0) STATE: SSB2" severity error;
                assert( a7_4 = 0 )      REPORT "Failed address(7 downto 4) STATE: SSB2" severity error;
                wait until clk'event and clk = '1';
                wait until clk'event and clk = '0';
            end if;
        end loop;

        --
        -- continue test bench
        --
        wait;
    end process;
end TB;

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configuration CFG_I8237A_TB of I8237A_TB is
    for TB
    end for;
end CFG_I8237A_TB;

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