top.vhd

硬件电子琴系统设计

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TOP IS                                     --顶层设计
    PORT (   CLK12MHZ : IN STD_LOGIC;
               INDEX1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
               CODE1  : OUT INTEGER RANGE 0 TO 15;
               HIGH1,SPKOUT  : OUT STD_LOGIC   );
 END;
ARCHITECTURE one OF TOP IS
       COMPONENT Tone
         PORT ( Index :  IN STD_LOGIC_VECTOR(7 DOWNTO 0);
                CODE  : OUT INTEGER RANGE 0 TO 15;
                HIGH  : OUT STD_LOGIC; 
															--11位2进制数
                Tone  : OUT INTEGER RANGE 0 TO 16#7FF#  ); 
    END COMPONENT;
    COMPONENT Speaker
        PORT( clk1  : IN STD_LOGIC;
               Tone1 : IN INTEGER RANGE 0 TO 16#7FF#;--11位2进制数
                 SpkS : OUT STD_LOGIC  );
    END COMPONENT;
    SIGNAL Tone2 : INTEGER RANGE 0 TO 16#7FF#;
  BEGIN                    -- 安装u1, u2
u1 : Tone    PORT MAP (Index=>Index1,Tone=>Tone2,
                            CODE=>CODE1,HIGH=>HIGH1);
u2 : Speaker PORT MAP (clk1=>CLK12MHZ,Tone1=>Tone2,
                            SpkS=>SPKOUT );
END;