rca_cy1c12_board.hif

RT8019网络控制器在FPGA中的驱动设计

data3
data4
data5
data6
data7
data8
data9
data10
data11
data12
data13
data14
data15
data16
data17
data18
data19
data20
data21
data22
data23
data24
data25
data26
data27
data28
data29
data30
data31
sel0
result0
result1
result2
result3
result4
result5
result6
result7
result8
result9
result10
result11
result12
result13
result14
result15
}
# end
# entity
sld_hub
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|sld_hub.vhd
1131032874
4
# storage
db|rca_cy1c12_board.(44).cnf
db|rca_cy1c12_board.(44).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
sld_hub_ip_version
1
PARAMETER_UNKNOWN
USR
sld_hub_ip_minor_version
2
PARAMETER_UNKNOWN
USR
sld_common_ip_version
0
PARAMETER_UNKNOWN
USR
device_family
Cyclone
PARAMETER_UNKNOWN
USR
n_nodes
1
PARAMETER_UNKNOWN
USR
n_sel_bits
1
PARAMETER_UNKNOWN
USR
n_node_ir_bits
4
PARAMETER_UNKNOWN
USR
node_info
00001100000000000110111000000000
PARAMETER_BIN
USR
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|sld_hub.vhd
1131032874
}
# end
# entity
sld_jtag_state_machine
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|sld_hub.vhd
1131032874
4
# storage
db|rca_cy1c12_board.(45).cnf
db|rca_cy1c12_board.(45).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
ip_major_version
1
PARAMETER_DEC
USR
ip_minor_version
2
PARAMETER_DEC
USR
common_ip_version
0
PARAMETER_DEC
USR
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|sld_hub.vhd
1131032874
}
# end
# entity
lpm_shiftreg
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|lpm_shiftreg.tdf
1114012454
6
# storage
db|rca_cy1c12_board.(46).cnf
db|rca_cy1c12_board.(46).cnf
# user_parameter {
LPM_WIDTH
10
PARAMETER_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
aclr
clock
enable
q0
q1
q2
q3
q4
q5
q6
q7
q8
q9
shiftin
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1131033050
c:|altera|quartus50|libraries|megafunctions|lpm_constant.inc
1107574524
c:|altera|quartus50|libraries|megafunctions|dffeea.inc
1107574164
}
# end
# entity
lpm_decode
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|lpm_decode.tdf
1114012450
6
# storage
db|rca_cy1c12_board.(47).cnf
db|rca_cy1c12_board.(47).cnf
# user_parameter {
LPM_WIDTH
3
PARAMETER_DEC
USR
LPM_DECODES
8
PARAMETER_DEC
USR
LPM_PIPELINE
1
PARAMETER_DEC
USR
CASCADE_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
decode_9ie
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
aclr
clken
clock
data0
data1
data2
enable
eq0
eq1
eq2
eq3
eq7
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1131033050
c:|altera|quartus50|libraries|megafunctions|lpm_constant.inc
1107574524
c:|altera|quartus50|libraries|megafunctions|declut.inc
1107574136
c:|altera|quartus50|libraries|megafunctions|altshift.inc
1107573438
c:|altera|quartus50|libraries|megafunctions|lpm_compare.inc
1107574500
}
# end
# entity
decode_9ie
# case_insensitive
# source_file
db|decode_9ie.tdf
1140411192
6
# storage
db|rca_cy1c12_board.(48).cnf
db|rca_cy1c12_board.(48).cnf
# used_port {
aclr
clken
clock
data0
data1
data2
enable
eq0
eq1
eq2
eq3
eq4
eq5
eq6
eq7
}
# end
# entity
sld_dffex
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|sld_dffex.vhd
1131032874
4
# storage
db|rca_cy1c12_board.(49).cnf
db|rca_cy1c12_board.(49).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
size
1
PARAMETER_DEC
USR
}
# end
# entity
sld_dffex
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|sld_dffex.vhd
1131032874
4
# storage
db|rca_cy1c12_board.(50).cnf
db|rca_cy1c12_board.(50).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
size
5
PARAMETER_DEC
USR
}
# end
# entity
sld_dffex
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|sld_dffex.vhd
1131032874
4
# storage
db|rca_cy1c12_board.(51).cnf
db|rca_cy1c12_board.(51).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
size
4
PARAMETER_DEC
USR
}
# end
# entity
sld_rom_sr
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|sld_rom_sr.vhd
1131032874
4
# storage
db|rca_cy1c12_board.(52).cnf
db|rca_cy1c12_board.(52).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
common_ip_version
0
PARAMETER_DEC
USR
n_bits
64
PARAMETER_DEC
USR
word_size
4
PARAMETER_DEC
USR
}
# end
# entity
rca_cy1c12_board_top
# case_insensitive
# source_file
rca_cy1c12_board_top.bdf
1145165379
23
# storage
db|rca_cy1c12_board.(0).cnf
db|rca_cy1c12_board.(0).cnf
# hierarchies {
|
}
# end
# entity
rca_cy1c12_board
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
rca_cy1c12_board.v
1145165347
7
# storage
db|rca_cy1c12_board.(1).cnf
db|rca_cy1c12_board.(1).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rca_cy1c12_board:inst
}
# end
# entity
asmi_asmi_control_port_arbitrator
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
rca_cy1c12_board.v
1145165347
7
# storage
db|rca_cy1c12_board.(2).cnf
db|rca_cy1c12_board.(2).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rca_cy1c12_board:inst|asmi_asmi_control_port_arbitrator:the_asmi_asmi_control_port
}
# end
# entity
asmi
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
asmi.v
1145165338
7
# storage
db|rca_cy1c12_board.(3).cnf
db|rca_cy1c12_board.(3).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rca_cy1c12_board:inst|asmi:the_asmi
}
# end
# entity
asmi_sub
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
asmi.v
1145165338
7
# storage
db|rca_cy1c12_board.(4).cnf
db|rca_cy1c12_board.(4).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rca_cy1c12_board:inst|asmi:the_asmi|asmi_sub:the_asmi_sub
}
# end
# entity
tornado_asmi_atom
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
asmi.v
1145165338
7
# storage
db|rca_cy1c12_board.(5).cnf
db|rca_cy1c12_board.(5).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rca_cy1c12_board:inst|asmi:the_asmi|tornado_asmi_atom:the_tornado_asmi_atom
}
# end
# entity
cpu_0_data_master_arbitrator
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
rca_cy1c12_board.v
1145165347
7
# storage
db|rca_cy1c12_board.(6).cnf
db|rca_cy1c12_board.(6).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rca_cy1c12_board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master
}
# end
# entity
cpu_0_instruction_master_arbitrator
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
rca_cy1c12_board.v
1145165347
7
# storage
db|rca_cy1c12_board.(7).cnf
db|rca_cy1c12_board.(7).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rca_cy1c12_board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master
}
# end
# entity
cpu_0
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
1145165328
7
# storage
db|rca_cy1c12_board.(8).cnf
db|rca_cy1c12_board.(8).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rca_cy1c12_board:inst|cpu_0:the_cpu_0
}
# end
# entity
cpu_0_test_bench
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0_test_bench.v
1145165327
7
# storage
db|rca_cy1c12_board.(9).cnf
db|rca_cy1c12_board.(9).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rca_cy1c12_board:inst|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench
}
# end
# entity
cpu_0_rf_module
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
1145165328
7
# storage
db|rca_cy1c12_board.(10).cnf
db|rca_cy1c12_board.(10).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
lpm_file
rf_ram.mif
PARAMETER_STRING
USR
}
# hierarchies {
rca_cy1c12_board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf
}
# end
# entity
altsyncram_dno1
# case_insensitive
# source_file
db|altsyncram_dno1.tdf
1140411181
6
# storage
db|rca_cy1c12_board.(12).cnf
db|rca_cy1c12_board.(12).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
wren_b
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
data_a8
data_a9
data_a10
data_a11
data_a12
data_a13
data_a14
data_a15
data_a16
data_a17
data_a18
data_a19
data_a20
data_a21
data_a22
data_a23
data_a24
data_a25
data_a26
data_a27
data_a28
data_a29
data_a30
data_a31
data_b0
data_b1
data_b2
data_b3
data_b4
data_b5
data_b6
data_b7
data_b8
data_b9
data_b10
data_b11
data_b12
data_b13
data_b14
data_b15
data_b16
data_b17
data_b18
data_b19
data_b20
data_b21
data_b22
data_b23
data_b24
data_b25
data_b26
data_b27
data_b28
data_b29
data_b30
data_b31
address_a0
address_a1
address_a2
address_a3
address_a4
address_b0
address_b1
address_b2
address_b3
address_b4
clock0
clock1
clocken0
clocken1
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_a8
q_a9
q_a10
q_a11
q_a12
q_a13
q_a14
q_a15
q_a16
q_a17
q_a18
q_a19
q_a20
q_a21
q_a22
q_a23
q_a24
q_a25
q_a26
q_a27
q_a28
q_a29
q_a30
q_a31
q_b0
q_b1
q_b2
q_b3
q_b4
q_b5
q_b6
q_b7
q_b8
q_b9
q_b10
q_b11
q_b12
q_b13
q_b14
q_b15
q_b16
q_b17
q_b18
q_b19
q_b20
q_b21
q_b22
q_b23
q_b24
q_b25
q_b26
q_b27
q_b28
q_b29
q_b30
q_b31
}
# memory_file {
rf_ram.mif
1145165326