rca_cy1c12_board.tan.qmsg

RT8019网络控制器在FPGA中的驱动设计

{ "Info" "ITDB_FULL_TPD_RESULT" "altera_internal_jtag~TDO altera_reserved_tdo 2.124 ns Longest " "Info: Longest tpd from source pin \"altera_internal_jtag~TDO\" to destination pin \"altera_reserved_tdo\" is 2.124 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TDO 1 PIN JTAG_X1_Y10_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 1; PIN Node = 'altera_internal_jtag~TDO'" {  } { { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.124 ns) 2.124 ns altera_reserved_tdo 2 PIN PIN_149 0 " "Info: 2: + IC(0.000 ns) + CELL(2.124 ns) = 2.124 ns; Loc. = PIN_149; Fanout = 0; PIN Node = 'altera_reserved_tdo'" {  } { { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "2.124 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns 100.00 % " "Info: Total cell delay = 2.124 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "2.124 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.124 ns" { altera_internal_jtag~TDO altera_reserved_tdo } { 0.000ns 0.000ns } { 0.000ns 2.124ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "sld_hub:sld_hub_inst\|lpm_shiftreg:jtag_ir_register\|dffs\[9\] altera_internal_jtag altera_internal_jtag~TCKUTAP 3.752 ns register " "Info: th for register \"sld_hub:sld_hub_inst\|lpm_shiftreg:jtag_ir_register\|dffs\[9\]\" (data pin = \"altera_internal_jtag\", clock pin = \"altera_internal_jtag~TCKUTAP\") is 3.752 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.292 ns + Longest register " "Info: + Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.292 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N1 96 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 96; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.581 ns) + CELL(0.711 ns) 5.292 ns sld_hub:sld_hub_inst\|lpm_shiftreg:jtag_ir_register\|dffs\[9\] 2 REG LC_X9_Y11_N4 2 " "Info: 2: + IC(4.581 ns) + CELL(0.711 ns) = 5.292 ns; Loc. = LC_X9_Y11_N4; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|lpm_shiftreg:jtag_ir_register\|dffs\[9\]'" {  } { { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[9] } "NODE_NAME" } "" } } { "lpm_shiftreg.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_shiftreg.tdf" 54 7 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 13.44 % " "Info: Total cell delay = 0.711 ns ( 13.44 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.581 ns 86.56 %