rca_cy1c12_board.tan.qmsg

RT8019网络控制器在FPGA中的驱动设计

{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off rca_cy1c12_board -c rca_cy1c12_board --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off rca_cy1c12_board -c rca_cy1c12_board --timing_analysis_only" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "PLD_CLOCKINPUT\[1\] " "Info: Assuming node \"PLD_CLOCKINPUT\[1\]\" is an undefined clock" {  } { { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 64 408 576 80 "PLD_CLOCKINPUT\[1\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "PLD_CLOCKINPUT\[1\]" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~TCKUTAP " "Info: Assuming node \"altera_internal_jtag~TCKUTAP\" is an undefined clock" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TCKUTAP" } } } }  } 0}  } {  } 0}