altsyncram_q201.tdf

RT8019网络控制器在FPGA中的驱动设计

--altsyncram BYTE_SIZE=8 CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" INIT_FILE="data_RAM.hex" NUMWORDS_A=256 OPERATION_MODE="SINGLE_PORT" OUTDATA_REG_A="UNREGISTERED" RAM_BLOCK_TYPE="M4K" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=32 WIDTH_BYTEENA_A=4 WIDTHAD_A=8 address_a byteena_a clock0 clocken0 data_a q_a wren_a
--VERSION_BEGIN 5.0 cbx_altsyncram 2005:11:01:19:33:48:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:11:01:14:36:46:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END


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PARAMETERS
(
	PORT_A_ADDRESS_WIDTH = 1,
	PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
	PORT_A_DATA_WIDTH = 1,
	PORT_B_ADDRESS_WIDTH = 1,
	PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
	PORT_B_DATA_WIDTH = 1
);
FUNCTION cyclone_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbrewe)
WITH ( 	CONNECTIVITY_CHECKING,	DATA_INTERLEAVE_OFFSET_IN_BITS,	DATA_INTERLEAVE_WIDTH_IN_BITS,	INIT_FILE,	INIT_FILE_LAYOUT,	LOGICAL_RAM_NAME,	mem_init0,	mem_init1,	MIXED_PORT_FEED_THROUGH_MODE,	OPERATION_MODE,	PORT_A_ADDRESS_CLEAR,	PORT_A_ADDRESS_WIDTH,	PORT_A_BYTE_ENABLE_CLEAR,	PORT_A_BYTE_ENABLE_MASK_WIDTH,	PORT_A_DATA_IN_CLEAR,	PORT_A_DATA_OUT_CLEAR,	PORT_A_DATA_OUT_CLOCK,	PORT_A_DATA_WIDTH,	PORT_A_FIRST_ADDRESS,	PORT_A_FIRST_BIT_NUMBER,	PORT_A_LAST_ADDRESS,	PORT_A_LOGICAL_RAM_DEPTH,	PORT_A_LOGICAL_RAM_WIDTH,	PORT_A_WRITE_ENABLE_CLEAR,	PORT_B_ADDRESS_CLEAR,	PORT_B_ADDRESS_CLOCK,	PORT_B_ADDRESS_WIDTH,	PORT_B_BYTE_ENABLE_CLEAR,	PORT_B_BYTE_ENABLE_CLOCK,	PORT_B_BYTE_ENABLE_MASK_WIDTH,	PORT_B_DATA_IN_CLEAR,	PORT_B_DATA_IN_CLOCK,	PORT_B_DATA_OUT_CLEAR,	PORT_B_DATA_OUT_CLOCK,	PORT_B_DATA_WIDTH,	PORT_B_FIRST_ADDRESS,	PORT_B_FIRST_BIT_NUMBER,	PORT_B_LAST_ADDRESS,	PORT_B_LOGICAL_RAM_DEPTH,	PORT_B_LOGICAL_RAM_WIDTH,	PORT_B_READ_ENABLE_WRITE_ENABLE_CLEAR,	PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK,	POWER_UP_UNINITIALIZED,	RAM_BLOCK_TYPE) 
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);

--synthesis_resources = M4K 2 
SUBDESIGN altsyncram_q201
( 
	address_a[7..0]	:	input;
	byteena_a[3..0]	:	input;
	clock0	:	input;
	clocken0	:	input;
	data_a[31..0]	:	input;
	q_a[31..0]	:	output;
	wren_a	:	input;
) 
VARIABLE 
	ram_block1a0 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "data_RAM.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 8,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 8,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 255,
			PORT_A_LOGICAL_RAM_DEPTH = 256,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block1a1 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "data_RAM.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 8,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 8,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 8,
			PORT_A_LAST_ADDRESS = 255,
			PORT_A_LOGICAL_RAM_DEPTH = 256,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block1a2 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "data_RAM.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 8,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 8,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 16,
			PORT_A_LAST_ADDRESS = 255,
			PORT_A_LOGICAL_RAM_DEPTH = 256,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			RAM_BLOCK_TYPE = "M4K"
		);
	ram_block1a3 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "data_RAM.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 8,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 8,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 24,
			PORT_A_LAST_ADDRESS = 255,
			PORT_A_LOGICAL_RAM_DEPTH = 256,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			RAM_BLOCK_TYPE = "M4K"
		);
	address_a_wire[7..0]	: WIRE;

BEGIN 
	ram_block1a[3..0].clk0 = clock0;
	ram_block1a[3..0].ena0 = clocken0;
	ram_block1a[0].portaaddr[] = ( address_a_wire[7..0]);
	ram_block1a[1].portaaddr[] = ( address_a_wire[7..0]);
	ram_block1a[2].portaaddr[] = ( address_a_wire[7..0]);
	ram_block1a[3].portaaddr[] = ( address_a_wire[7..0]);
	ram_block1a[0].portabyteenamasks[] = ( byteena_a[0..0]);
	ram_block1a[1].portabyteenamasks[] = ( byteena_a[1..1]);
	ram_block1a[2].portabyteenamasks[] = ( byteena_a[2..2]);
	ram_block1a[3].portabyteenamasks[] = ( byteena_a[3..3]);
	ram_block1a[0].portadatain[] = ( data_a[7..0]);
	ram_block1a[1].portadatain[] = ( data_a[15..8]);
	ram_block1a[2].portadatain[] = ( data_a[23..16]);
	ram_block1a[3].portadatain[] = ( data_a[31..24]);
	ram_block1a[3..0].portawe = wren_a;
	address_a_wire[] = address_a[];
	q_a[] = ( ram_block1a[3..0].portadataout[7..0]);
END;
--VALID FILE