rca_cy1c12_board.map.qmsg

RT8019网络控制器在FPGA中的驱动设计

{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 asmi.v(356) " "Warning: Verilog HDL assignment warning at asmi.v(356): truncated value with size 32 to match size of target (1)" {  } { { "asmi.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/asmi.v" 356 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 asmi.v(360) " "Warning: Verilog HDL assignment warning at asmi.v(360): truncated value with size 32 to match size of target (1)" {  } { { "asmi.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/asmi.v" 360 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 asmi.v(364) " "Warning: Verilog HDL assignment warning at asmi.v(364): truncated value with size 32 to match size of target (1)" {  } { { "asmi.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/asmi.v" 364 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 asmi.v(368) " "Warning: Verilog HDL assignment warning at asmi.v(368): truncated value with size 32 to match size of target (1)" {  } { { "asmi.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/asmi.v" 368 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 asmi.v(372) " "Warning: Verilog HDL assignment warning at asmi.v(372): truncated value with size 32 to match size of target (1)" {  } { { "asmi.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/asmi.v" 372 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 asmi.v(376) " "Warning: Verilog HDL assignment warning at asmi.v(376): truncated value with size 32 to match size of target (1)" {  } { { "asmi.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/asmi.v" 376 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 asmi.v(381) " "Warning: Verilog HDL assignment warning at asmi.v(381): truncated value with size 32 to match size of target (1)" {  } { { "asmi.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/asmi.v" 381 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 asmi.v(383) " "Warning: Verilog HDL assignment warning at asmi.v(383): truncated value with size 32 to match size of target (1)" {  } { { "asmi.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/asmi.v" 383 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 asmi.v(384) " "Warning: Verilog HDL assignment warning at asmi.v(384): truncated value with size 32 to match size of target (1)" {  } { { "asmi.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/asmi.v" 384 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 asmi.v(385) " "Warning: Verilog HDL assignment warning at asmi.v(385): truncated value with size 32 to match size of target (1)" {  } { { "asmi.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/asmi.v" 385 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 asmi.v(391) " "Warning: Verilog HDL assignment warning at asmi.v(391): truncated value with size 32 to match size of target (1)" {  } { { "asmi.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/asmi.v" 391 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 asmi.v(392) " "Warning: Verilog HDL assignment warning at asmi.v(392): truncated value with size 32 to match size of target (1)" {  } { { "asmi.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/asmi.v" 392 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 asmi.v(394) " "Warning: Verilog HDL assignment warning at asmi.v(394): truncated value with size 32 to match size of target (1)" {  } { { "asmi.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/asmi.v" 394 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 asmi.v(396) " "Warning: Verilog HDL assignment warning at asmi.v(396): truncated value with size 32 to match size of target (1)" {  } { { "asmi.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/asmi.v" 396 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "asmi.v(403) " "Warning: (10037) Verilog HDL or VHDL warning at asmi.v(403): condition expression evaluates to a constant" {  } { { "asmi.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/asmi.v" 403 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tornado_asmi_atom rca_cy1c12_board:inst\|asmi:the_asmi\|tornado_asmi_atom:the_tornado_asmi_atom " "Info: Elaborating entity \"tornado_asmi_atom\" for hierarchy \"rca_cy1c12_board:inst\|asmi:the_asmi\|tornado_asmi_atom:the_tornado_asmi_atom\"" {  } { { "asmi.v" "the_tornado_asmi_atom" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/asmi.v" 529 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_data_master_arbitrator rca_cy1c12_board:inst\|cpu_0_data_master_arbitrator:the_cpu_0_data_master " "Info: Elaborating entity \"cpu_0_data_master_arbitrator\" for hierarchy \"rca_cy1c12_board:inst\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\"" {  } { { "rca_cy1c12_board.v" "the_cpu_0_data_master" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 3503 -1 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rca_cy1c12_board.v(434) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(434): truncated value with size 32 to match size of target (1)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 434 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rca_cy1c12_board.v(440) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(440): truncated value with size 32 to match size of target (1)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 440 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "23 1 rca_cy1c12_board.v(446) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(446): truncated value with size 23 to match size of target (1)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 446 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rca_cy1c12_board.v(495) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(495): truncated value with size 32 to match size of target (1)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 495 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "rca_cy1c12_board.v(496) " "Warning: (10037) Verilog HDL or VHDL warning at rca_cy1c12_board.v(496): condition expression evaluates to a constant" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 496 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rca_cy1c12_board.v(497) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(497): truncated value with size 32 to match size of target (1)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 497 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "rca_cy1c12_board.v(543) " "Warning: (10037) Verilog HDL or VHDL warning at rca_cy1c12_board.v(543): condition expression evaluates to a constant" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 543 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rca_cy1c12_board.v(555) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(555): truncated value with size 32 to match size of target (1)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 555 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "rca_cy1c12_board.v(556) " "Warning: (10037) Verilog HDL or VHDL warning at rca_cy1c12_board.v(556): condition expression evaluates to a constant" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 556 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rca_cy1c12_board.v(566) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(566): truncated value with size 32 to match size of target (1)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 566 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 rca_cy1c12_board.v(581) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(581): truncated value with size 32 to match size of target (16)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 581 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 rca_cy1c12_board.v(594) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(594): truncated value with size 32 to match size of target (2)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 594 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 rca_cy1c12_board.v(612) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(612): truncated value with size 32 to match size of target (2)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 612 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_instruction_master_arbitrator rca_cy1c12_board:inst\|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master " "Info: Elaborating entity \"cpu_0_instruction_master_arbitrator\" for hierarchy \"rca_cy1c12_board:inst\|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master\"" {  } { { "rca_cy1c12_board.v" "the_cpu_0_instruction_master" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 3541 -1 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "active_and_waiting_last_time rca_cy1c12_board.v(699) " "Info: (10035) Verilog HDL or VHDL information at rca_cy1c12_board.v(699): object \"active_and_waiting_last_time\" declared but not used" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 699 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "cpu_0_instruction_master_address_last_time rca_cy1c12_board.v(700) " "Info: (10035) Verilog HDL or VHDL information at rca_cy1c12_board.v(700): object \"cpu_0_instruction_master_address_last_time\" declared but not used" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 700 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "cpu_0_instruction_master_read_last_time rca_cy1c12_board.v(704) " "Info: (10035) Verilog HDL or VHDL information at rca_cy1c12_board.v(704): object \"cpu_0_instruction_master_read_last_time\" declared but not used" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 704 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rca_cy1c12_board.v(718) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(718): truncated value with size 32 to match size of target (1)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 718 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rca_cy1c12_board.v(724) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(724): truncated value with size 32 to match size of target (1)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 724 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "23 1 rca_cy1c12_board.v(730) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(730): truncated value with size 23 to match size of target (1)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 730 0 0 } }  } 0}