rca_cy1c12_board.map.qmsg

RT8019网络控制器在FPGA中的驱动设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 19 14:31:43 2006 " "Info: Processing started: Wed Apr 19 14:31:43 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off rca_cy1c12_board -c rca_cy1c12_board " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off rca_cy1c12_board -c rca_cy1c12_board" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rca_cy1c12_board_top.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file rca_cy1c12_board_top.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 rca_cy1c12_board_top " "Info: Found entity 1: rca_cy1c12_board_top" {  } { { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "rca_cy1c12_board_top " "Info: Elaborating entity \"rca_cy1c12_board_top\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "rca_cy1c12_board.v 15 15 " "Info: Using design file rca_cy1c12_board.v, which is not specified as a design file for the current project, but contains definitions for 15 design units and 15 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 asmi_asmi_control_port_arbitrator " "Info: Found entity 1: asmi_asmi_control_port_arbitrator" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 21 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 cpu_0_data_master_arbitrator " "Info: Found entity 2: cpu_0_data_master_arbitrator" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 270 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "3 cpu_0_instruction_master_arbitrator " "Info: Found entity 3: cpu_0_instruction_master_arbitrator" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 624 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "4 data_RAM_s1_arbitrator " "Info: Found entity 4: data_RAM_s1_arbitrator" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 866 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "5 firmware_ROM_s1_arbitrator " "Info: Found entity 5: firmware_ROM_s1_arbitrator" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 1265 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "6 jtag_uart_0_avalon_jtag_slave_arbitrator " "Info: Found entity 6: jtag_uart_0_avalon_jtag_slave_arbitrator" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 1664 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "7 payload_buffer_s1_arbitrator " "Info: Found entity 7: payload_buffer_s1_arbitrator" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 1915 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "8 sysid_control_slave_arbitrator " "Info: Found entity 8: sysid_control_slave_arbitrator" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 2336 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "9 tri_state_bridge_0_avalon_slave_arbitrator " "Info: Found entity 9: tri_state_bridge_0_avalon_slave_arbitrator" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 2523 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "10 tri_state_bridge_0_bridge_arbitrator " "Info: Found entity 10: tri_state_bridge_0_bridge_arbitrator" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 3171 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "11 rca_cy1c12_board_reset_clk_domain_synch_module " "Info: Found entity 11: rca_cy1c12_board_reset_clk_domain_synch_module" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 3179 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "12 rca_cy1c12_board " "Info: Found entity 12: rca_cy1c12_board" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 3219 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "13 ext_flash_lane0_module " "Info: Found entity 13: ext_flash_lane0_module" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 3826 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "14 ext_flash_lane1_module " "Info: Found entity 14: ext_flash_lane1_module" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 3912 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "15 ext_flash " "Info: Found entity 15: ext_flash" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 3998 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rca_cy1c12_board rca_cy1c12_board:inst " "Info: Elaborating entity \"rca_cy1c12_board\" for hierarchy \"rca_cy1c12_board:inst\"" {  } { { "rca_cy1c12_board_top.bdf" "inst" { Schematic "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 40 632 896 216 "inst" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rca_cy1c12_board.v(3815) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(3815): truncated value with size 32 to match size of target (1)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 3815 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rca_cy1c12_board.v(3819) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(3819): truncated value with size 32 to match size of target (1)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 3819 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asmi_asmi_control_port_arbitrator rca_cy1c12_board:inst\|asmi_asmi_control_port_arbitrator:the_asmi_asmi_control_port " "Info: Elaborating entity \"asmi_asmi_control_port_arbitrator\" for hierarchy \"rca_cy1c12_board:inst\|asmi_asmi_control_port_arbitrator:the_asmi_asmi_control_port\"" {  } { { "rca_cy1c12_board.v" "the_asmi_asmi_control_port" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 3416 -1 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rca_cy1c12_board.v(127) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(127): truncated value with size 32 to match size of target (1)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 127 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "rca_cy1c12_board.v(128) " "Warning: (10037) Verilog HDL or VHDL warning at rca_cy1c12_board.v(128): condition expression evaluates to a constant" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 128 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 rca_cy1c12_board.v(145) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(145): truncated value with size 32 to match size of target (2)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 145 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 rca_cy1c12_board.v(148) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(148): truncated value with size 32 to match size of target (2)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 148 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 rca_cy1c12_board.v(163) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(163): truncated value with size 32 to match size of target (2)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 163 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rca_cy1c12_board.v(173) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(173): truncated value with size 32 to match size of target (1)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 173 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rca_cy1c12_board.v(183) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(183): truncated value with size 32 to match size of target (1)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 183 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rca_cy1c12_board.v(186) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(186): truncated value with size 32 to match size of target (1)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 186 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 rca_cy1c12_board.v(190) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(190): truncated value with size 32 to match size of target (16)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 190 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rca_cy1c12_board.v(202) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(202): truncated value with size 32 to match size of target (1)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 202 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rca_cy1c12_board.v(205) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(205): truncated value with size 32 to match size of target (1)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 205 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rca_cy1c12_board.v(208) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(208): truncated value with size 32 to match size of target (1)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 208 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "23 3 rca_cy1c12_board.v(230) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(230): truncated value with size 23 to match size of target (3)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 230 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rca_cy1c12_board.v(236) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(236): truncated value with size 32 to match size of target (1)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 236 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "rca_cy1c12_board.v(237) " "Warning: (10037) Verilog HDL or VHDL warning at rca_cy1c12_board.v(237): condition expression evaluates to a constant" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 237 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rca_cy1c12_board.v(260) " "Warning: Verilog HDL assignment warning at rca_cy1c12_board.v(260): truncated value with size 32 to match size of target (1)" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 260 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "cpu_0_data_master_read_data_valid_asmi_asmi_control_port rca_cy1c12_board.v(67) " "Warning: Output port \"cpu_0_data_master_read_data_valid_asmi_asmi_control_port\" at rca_cy1c12_board.v(67) has no driver" {  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 67 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "asmi.v 3 3 " "Info: Using design file asmi.v, which is not specified as a design file for the current project, but contains definitions for 3 design units and 3 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 asmi_sub " "Info: Found entity 1: asmi_sub" {  } { { "asmi.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/asmi.v" 36 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 tornado_asmi_atom " "Info: Found entity 2: tornado_asmi_atom" {  } { { "asmi.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/asmi.v" 418 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "3 asmi " "Info: Found entity 3: asmi" {  } { { "asmi.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/asmi.v" 461 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asmi rca_cy1c12_board:inst\|asmi:the_asmi " "Info: Elaborating entity \"asmi\" for hierarchy \"rca_cy1c12_board:inst\|asmi:the_asmi\"" {  } { { "rca_cy1c12_board.v" "the_asmi" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 3432 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asmi_sub rca_cy1c12_board:inst\|asmi:the_asmi\|asmi_sub:the_asmi_sub " "Info: Elaborating entity \"asmi_sub\" for hierarchy \"rca_cy1c12_board:inst\|asmi:the_asmi\|asmi_sub:the_asmi_sub\"" {  } { { "asmi.v" "the_asmi_sub" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/asmi.v" 519 -1 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 asmi.v(138) " "Warning: Verilog HDL assignment warning at asmi.v(138): truncated value with size 32 to match size of target (1)" {  } { { "asmi.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/asmi.v" 138 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "asmi.v(139) " "Warning: (10037) Verilog HDL or VHDL warning at asmi.v(139): condition expression evaluates to a constant" {  } { { "asmi.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/asmi.v" 139 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 asmi.v(148) " "Warning: Verilog HDL assignment warning at asmi.v(148): truncated value with size 32 to match size of target (1)" {  } { { "asmi.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/asmi.v" 148 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "asmi.v(149) " "Warning: (10037) Verilog HDL or VHDL warning at asmi.v(149): condition expression evaluates to a constant" {  } { { "asmi.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/asmi.v" 149 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 asmi.v(159) " "Warning: Verilog HDL assignment warning at asmi.v(159): truncated value with size 32 to match size of target (1)" {  } { { "asmi.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/asmi.v" 159 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "asmi.v(160) " "Warning: (10037) Verilog HDL or VHDL warning at asmi.v(160): condition expression evaluates to a constant" {  } { { "asmi.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/asmi.v" 160 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 asmi.v(169) " "Warning: Verilog HDL assignment warning at asmi.v(169): truncated value with size 32 to match size of target (1)" {  } { { "asmi.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/asmi.v" 169 0 0 } }  } 0}