cntr_9c7.tdf

RT8019网络控制器在FPGA中的驱动设计

--lpm_counter DEVICE_FAMILY="Cyclone" lpm_width=6 aclr clock cnt_en q sclr updown
--VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:11:01:14:36:46:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END


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--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
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--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.


FUNCTION cyclone_lcell (aclr, aload, cin, clk, dataa, datab, datac, datad, ena, inverta, regcascin, sclr, sload)
WITH ( 	cin_used,	lut_mask,	operation_mode,	output_mode,	register_cascade_mode,	sum_lutc_input,	synch_mode) 
RETURNS ( combout, cout, regout);

--synthesis_resources = lut 6 
SUBDESIGN cntr_9c7
( 
	aclr	:	input;
	clock	:	input;
	cnt_en	:	input;
	cout	:	output;
	q[5..0]	:	output;
	sclr	:	input;
	updown	:	input;
) 
VARIABLE 
	counter_cella0 : cyclone_lcell
		WITH (
			cin_used = "false",
			lut_mask = "5599",
			operation_mode = "arithmetic",
			synch_mode = "on"
		);
	counter_cella1 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "5A90",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella2 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "5A90",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella3 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "5A90",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella4 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "5A90",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	counter_cella5 : cyclone_lcell
		WITH (
			cin_used = "true",
			lut_mask = "5A90",
			operation_mode = "arithmetic",
			sum_lutc_input = "cin",
			synch_mode = "on"
		);
	a_val[5..0]	: WIRE;
	aclr_actual	: WIRE;
	aset_node	: WIRE;
	clk_en	: NODE;
	data[5..0]	: NODE;
	s_val[5..0]	: WIRE;
	safe_q[5..0]	: WIRE;
	sload	: NODE;
	sset	: NODE;
	sset_node	: WIRE;
	time_to_clear	: WIRE;
	updownDir	: WIRE;

BEGIN 
	counter_cella[5..0].aclr = aclr_actual;
	counter_cella[5..0].aload = B"000000";
	counter_cella[1].cin = counter_cella[0].cout;
	counter_cella[2].cin = counter_cella[1].cout;
	counter_cella[3].cin = counter_cella[2].cout;
	counter_cella[4].cin = counter_cella[3].cout;
	counter_cella[5].cin = counter_cella[4].cout;
	counter_cella[5..0].clk = clock;
	counter_cella[5..0].dataa = safe_q[];
	counter_cella[5..0].datab = updownDir;
	counter_cella[5..0].datac = ((sset & s_val[]) # ((! sset) & data[]));
	counter_cella[5..0].ena = (clk_en & (((cnt_en # sclr) # sset) # sload));
	counter_cella[5..0].sclr = sclr;
	counter_cella[5..0].sload = (sset # sload);
	a_val[] = B"111111";
	aclr_actual = aclr;
	aset_node = B"0";
	clk_en = VCC;
	cout = counter_cella[5].cout;
	data[] = GND;
	q[] = safe_q[];
	s_val[] = B"111111";
	safe_q[] = counter_cella[5..0].regout;
	sload = GND;
	sset = GND;
	sset_node = B"0";
	time_to_clear = B"0";
	updownDir = updown;
END;
--VALID FILE