rca_cy1c12_board.fit.qmsg

RT8019网络控制器在FPGA中的驱动设计

{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "rca_cy1c12_board:inst\|rca_cy1c12_board_reset_clk_domain_synch_module:rca_cy1c12_board_reset_clk_domain_synch\|data_out " "Info: Node rca_cy1c12_board:inst\|rca_cy1c12_board_reset_clk_domain_synch_module:rca_cy1c12_board_reset_clk_domain_synch\|data_out uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|rvalid " "Info: Port clear -- assigned as a global for destination node rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|rvalid -- routed using non-global resources" {  } { { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "" { rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rvalid } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|rvalid" } } } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_jtag_atlantic.v" 197 -1 0 } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rvalid } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|t_dav " "Info: Port clear -- assigned as a global for destination node rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|t_dav -- routed using non-global resources" {  } { { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "" { rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|t_dav } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|t_dav" } } } } { "jtag_uart_0.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/jtag_uart_0.v" 539 -1 0 } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|t_dav } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|read_write2 " "Info: Port clear -- assigned as a global for destination node rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|read_write2 -- routed using non-global resources" {  } { { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "" { rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|read_write2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|read_write2" } } } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_jtag_atlantic.v" 202 -1 0 } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|read_write2 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate2 " "Info: Port clear -- assigned as a global for destination node rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate2 -- routed using non-global resources" {  } { { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "" { rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate2" } } } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_jtag_atlantic.v" 205 -1 0 } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate2 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|t_pause~reg0 " "Info: Port clear -- assigned as a global for destination node rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|t_pause~reg0 -- routed using non-global resources" {  } { { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "" { rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|t_pause~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|t_pause~reg0" } } } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_jtag_atlantic.v" 412 -1 0 } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|t_pause~reg0 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|read_write1 " "Info: Port clear -- assigned as a global for destination node rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|read_write1 -- routed using non-global resources" {  } { { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "" { rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|read_write1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|read_write1" } } } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_jtag_atlantic.v" 201 -1 0 } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|read_write1 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate1 " "Info: Port clear -- assigned as a global for destination node rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate1 -- routed using non-global resources" {  } { { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "" { rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate1" } } } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_jtag_atlantic.v" 204 -1 0 } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate1 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear rca_cy1c12_board:inst\|cpu_0:the_cpu_0\|E_valid " "Info: Port clear -- assigned as a global for destination node rca_cy1c12_board:inst\|cpu_0:the_cpu_0\|E_valid -- routed using non-global resources" {  } { { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "" { rca_cy1c12_board:inst|cpu_0:the_cpu_0|E_valid } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rca_cy1c12_board:inst\|cpu_0:the_cpu_0\|E_valid" } } } } { "cpu_0.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/cpu_0.v" 352 -1 0 } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { rca_cy1c12_board:inst|cpu_0:the_cpu_0|E_valid } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear rca_cy1c12_board:inst\|cpu_0:the_cpu_0\|R_wr_dst_reg " "Info: Port clear -- assigned as a global for destination node rca_cy1c12_board:inst\|cpu_0:the_cpu_0\|R_wr_dst_reg -- routed using non-global resources" {  } { { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "" { rca_cy1c12_board:inst|cpu_0:the_cpu_0|R_wr_dst_reg } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rca_cy1c12_board:inst\|cpu_0:the_cpu_0\|R_wr_dst_reg" } } } } { "cpu_0.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/cpu_0.v" 579 -1 0 } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { rca_cy1c12_board:inst|cpu_0:the_cpu_0|R_wr_dst_reg } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear rca_cy1c12_board:inst\|cpu_0:the_cpu_0\|W_valid " "Info: Port clear -- assigned as a global for destination node rca_cy1c12_board:inst\|cpu_0:the_cpu_0\|W_valid -- routed using non-global resources" {  } { { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "" { rca_cy1c12_board:inst|cpu_0:the_cpu_0|W_valid } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rca_cy1c12_board:inst\|cpu_0:the_cpu_0\|W_valid" } } } } { "cpu_0.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/cpu_0.v" 600 -1 0 } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { rca_cy1c12_board:inst|cpu_0:the_cpu_0|W_valid } "NODE_NAME" } }  } 0}  } { { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "" { rca_cy1c12_board:inst|rca_cy1c12_board_reset_clk_domain_synch_module:rca_cy1c12_board_reset_clk_domain_synch|data_out } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rca_cy1c12_board:inst\|rca_cy1c12_board_reset_clk_domain_synch_module:rca_cy1c12_board_reset_clk_domain_synch\|data_out" } } } } { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 3189 -1 0 } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { rca_cy1c12_board:inst|rca_cy1c12_board_reset_clk_domain_synch_module:rca_cy1c12_board_reset_clk_domain_synch|data_out } "NODE_NAME" } }  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "4 " "Warning: The following 4 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_CE_N VCC " "Info: Pin SRAM_CE_N has VCC driving its datain port" {  } { { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 304 736 912 320 "SRAM_CE_N" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "" { SRAM_CE_N } "NODE_NAME" } "" } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { SRAM_CE_N } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_WE_N VCC " "Info: Pin SRAM_WE_N has VCC driving its datain port" {  } { { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 320 736 912 336 "SRAM_WE_N" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "" { SRAM_WE_N } "NODE_NAME" } "" } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { SRAM_WE_N } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SRAM_OE_N VCC " "Info: Pin SRAM_OE_N has VCC driving its datain port" {  } { { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 336 736 912 352 "SRAM_OE_N" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "" { SRAM_OE_N } "NODE_NAME" } "" } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { SRAM_OE_N } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FLASH_A\[0\] GND " "Info: Pin FLASH_A\[0\] has GND driving its datain port" {  } { { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 128 928 1104 144 "FLASH_A\[21..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FLASH_A\[0\]" } } } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "" { FLASH_A[0] } "NODE_NAME" } "" } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { FLASH_A[0] } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: The following groups of pins have the same output enable" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP" "rca_cy1c12_board:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|ext_flash_s1_in_a_write_cycle " "Info: The following pins have the same output enable: rca_cy1c12_board:inst\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|ext_flash_s1_in_a_write_cycle" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FLASH_D\[15\] LVTTL " "Info: Type bidirectional pin FLASH_D\[15\] uses the LVTTL I/O standard" {  } { { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 144 928 1104 160 "FLASH_D\[15..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FLASH_D\[15\]" } } } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "" { FLASH_D[15] } "NODE_NAME" } "" } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { FLASH_D[15] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FLASH_D\[14\] LVTTL " "Info: Type bidirectional pin FLASH_D\[14\] uses the LVTTL I/O standard" {  } { { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 144 928 1104 160 "FLASH_D\[15..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FLASH_D\[14\]" } } } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "" { FLASH_D[14] } "NODE_NAME" } "" } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { FLASH_D[14] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FLASH_D\[13\] LVTTL " "Info: Type bidirectional pin FLASH_D\[13\] uses the LVTTL I/O standard" {  } { { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 144 928 1104 160 "FLASH_D\[15..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FLASH_D\[13\]" } } } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "" { FLASH_D[13] } "NODE_NAME" } "" } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { FLASH_D[13] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FLASH_D\[12\] LVTTL " "Info: Type bidirectional pin FLASH_D\[12\] uses the LVTTL I/O standard" {  } { { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 144 928 1104 160 "FLASH_D\[15..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FLASH_D\[12\]" } } } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "" { FLASH_D[12] } "NODE_NAME" } "" } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { FLASH_D[12] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FLASH_D\[11\] LVTTL " "Info: Type bidirectional pin FLASH_D\[11\] uses the LVTTL I/O standard" {  } { { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 144 928 1104 160 "FLASH_D\[15..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FLASH_D\[11\]" } } } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "" { FLASH_D[11] } "NODE_NAME" } "" } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { FLASH_D[11] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FLASH_D\[10\] LVTTL " "Info: Type bidirectional pin FLASH_D\[10\] uses the LVTTL I/O standard" {  } { { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 144 928 1104 160 "FLASH_D\[15..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FLASH_D\[10\]" } } } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "" { FLASH_D[10] } "NODE_NAME" } "" } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { FLASH_D[10] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FLASH_D\[9\] LVTTL " "Info: Type bidirectional pin FLASH_D\[9\] uses the LVTTL I/O standard" {  } { { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 144 928 1104 160 "FLASH_D\[15..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FLASH_D\[9\]" } } } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "" { FLASH_D[9] } "NODE_NAME" } "" } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { FLASH_D[9] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FLASH_D\[8\] LVTTL " "Info: Type bidirectional pin FLASH_D\[8\] uses the LVTTL I/O standard" {  } { { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 144 928 1104 160 "FLASH_D\[15..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FLASH_D\[8\]" } } } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "" { FLASH_D[8] } "NODE_NAME" } "" } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { FLASH_D[8] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FLASH_D\[7\] LVTTL " "Info: Type bidirectional pin FLASH_D\[7\] uses the LVTTL I/O standard" {  } { { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 144 928 1104 160 "FLASH_D\[15..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FLASH_D\[7\]" } } } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "" { FLASH_D[7] } "NODE_NAME" } "" } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { FLASH_D[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FLASH_D\[6\] LVTTL " "Info: Type bidirectional pin FLASH_D\[6\] uses the LVTTL I/O standard" {  } { { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 144 928 1104 160 "FLASH_D\[15..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FLASH_D\[6\]" } } } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "" { FLASH_D[6] } "NODE_NAME" } "" } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { FLASH_D[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FLASH_D\[5\] LVTTL " "Info: Type bidirectional pin FLASH_D\[5\] uses the LVTTL I/O standard" {  } { { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 144 928 1104 160 "FLASH_D\[15..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FLASH_D\[5\]" } } } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "" { FLASH_D[5] } "NODE_NAME" } "" } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { FLASH_D[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FLASH_D\[4\] LVTTL " "Info: Type bidirectional pin FLASH_D\[4\] uses the LVTTL I/O standard" {  } { { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 144 928 1104 160 "FLASH_D\[15..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FLASH_D\[4\]" } } } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "" { FLASH_D[4] } "NODE_NAME" } "" } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { FLASH_D[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FLASH_D\[3\] LVTTL " "Info: Type bidirectional pin FLASH_D\[3\] uses the LVTTL I/O standard" {  } { { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 144 928 1104 160 "FLASH_D\[15..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FLASH_D\[3\]" } } } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "" { FLASH_D[3] } "NODE_NAME" } "" } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { FLASH_D[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FLASH_D\[2\] LVTTL " "Info: Type bidirectional pin FLASH_D\[2\] uses the LVTTL I/O standard" {  } { { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 144 928 1104 160 "FLASH_D\[15..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FLASH_D\[2\]" } } } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "" { FLASH_D[2] } "NODE_NAME" } "" } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { FLASH_D[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FLASH_D\[1\] LVTTL " "Info: Type bidirectional pin FLASH_D\[1\] uses the LVTTL I/O standard" {  } { { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 144 928 1104 160 "FLASH_D\[15..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FLASH_D\[1\]" } } } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "" { FLASH_D[1] } "NODE_NAME" } "" } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { FLASH_D[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FLASH_D\[0\] LVTTL " "Info: Type bidirectional pin FLASH_D\[0\] uses the LVTTL I/O standard" {  } { { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 144 928 1104 160 "FLASH_D\[15..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FLASH_D\[0\]" } } } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "" { FLASH_D[0] } "NODE_NAME" } "" } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { FLASH_D[0] } "NODE_NAME" } }  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 19 14:33:14 2006 " "Info: Processing ended: Wed Apr 19 14:33:14 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:38 " "Info: Elapsed time: 00:00:38" {  } {  } 0}  } {  } 0}