rca_cy1c12_board.fit.qmsg

RT8019网络控制器在FPGA中的驱动设计

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.467 ns register register " "Info: Estimated most critical path is register to register delay of 3.467 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 1 REG LAB_X9_Y11 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X9_Y11; Fanout = 10; REG Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode_usr1'" {  } { { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 381 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.910 ns) + CELL(0.590 ns) 1.500 ns rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|always0~48 2 COMB LAB_X10_Y12 4 " "Info: 2: + IC(0.910 ns) + CELL(0.590 ns) = 1.500 ns; Loc. = LAB_X10_Y12; Fanout = 4; COMB Node = 'rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|always0~48'" {  } { { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "1.500 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|always0~48 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.222 ns) + CELL(0.442 ns) 2.164 ns rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate~0 3 COMB LAB_X10_Y12 1 " "Info: 3: + IC(0.222 ns) + CELL(0.442 ns) = 2.164 ns; Loc. = LAB_X10_Y12; Fanout = 1; COMB Node = 'rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate~0'" {  } { { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "0.664 ns" { rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|always0~48 rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate~0 } "NODE_NAME" } "" } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_jtag_atlantic.v" 203 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.436 ns) + CELL(0.867 ns) 3.467 ns rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate 4 REG LAB_X10_Y12 2 " "Info: 4: + IC(0.436 ns) + CELL(0.867 ns) = 3.467 ns; Loc. = LAB_X10_Y12; Fanout = 2; REG Node = 'rca_cy1c12_board:inst\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate'" {  } { { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "1.303 ns" { rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate~0 rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate } "NODE_NAME" } "" } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_jtag_atlantic.v" 203 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.899 ns 54.77 % " "Info: Total cell delay = 1.899 ns ( 54.77 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.568 ns 45.23 % " "Info: Total interconnect delay = 1.568 ns ( 45.23 % )" {  } {  } 0}  } { { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "3.467 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|always0~48 rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate~0 rca_cy1c12_board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:04 " "Info: Fitter placement operations ending: elapsed time is 00:00:04" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "14 42 " "Info: Average interconnect usage is 14% of the available device resources. Peak interconnect usage is 42%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:04 " "Info: Fitter routing operations ending: elapsed time is 00:00:04" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}