rca_cy1c12_board.fit.qmsg

RT8019网络控制器在FPGA中的驱动设计

{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "PLD_CLOCKINPUT\[1\] Global clock in PIN 153 " "Info: Automatically promoted signal \"PLD_CLOCKINPUT\[1\]\" to use Global clock in PIN 153" {  } { { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 64 408 576 80 "PLD_CLOCKINPUT\[1\]" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "altera_internal_jtag~TCKUTAP Global clock " "Info: Automatically promoted signal \"altera_internal_jtag~TCKUTAP\" to use Global clock" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TDO" } } } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" "" { Report "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board_cmp.qrpt" Compiler "rca_cy1c12_board" "UNKNOWN" "V1" "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/db/rca_cy1c12_board.quartus_db" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } "" } } { "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" { Floorplan "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "PLD_CLEAR_N Global clock in PIN 131 " "Info: Automatically promoted signal \"PLD_CLEAR_N\" to use Global clock in PIN 131" {  } { { "rca_cy1c12_board_top.bdf" "" { Schematic "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board_top.bdf" { { 80 408 576 96 "PLD_CLEAR_N" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "rca_cy1c12_board:inst\|rca_cy1c12_board_reset_clk_domain_synch_module:rca_cy1c12_board_reset_clk_domain_synch\|data_out Global clock " "Info: Automatically promoted some destinations of signal \"rca_cy1c12_board:inst\|rca_cy1c12_board_reset_clk_domain_synch_module:rca_cy1c12_board_reset_clk_domain_synch\|data_out\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rca_cy1c12_board:inst\|cpu_0:the_cpu_0\|W_rf_wren_a " "Info: Destination \"rca_cy1c12_board:inst\|cpu_0:the_cpu_0\|W_rf_wren_a\" may be non-global or may not use global clock" {  } { { "cpu_0.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/cpu_0.v" 595 -1 0 } }  } 0}  } { { "rca_cy1c12_board.v" "" { Text "E:/code/EP1C6/l_standard/rca_cy1c12_board/system/rca_cy1c12_board.v" 3189 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "sld_hub:sld_hub_inst\|CLEAR_SIGNAL~0 Global clock " "Info: Automatically promoted signal \"sld_hub:sld_hub_inst\|CLEAR_SIGNAL~0\" to use Global clock" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 307 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] Global clock " "Info: Automatically promoted some destinations of signal \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[1\] " "Info: Destination \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[1\]\" may be non-global or may not use global clock" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 1014 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] " "Info: Destination \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]\" may be non-global or may not use global clock" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 1014 -1 0 } }  } 0}  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 1014 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|clear_signal Global clock " "Info: Automatically promoted signal \"sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|clear_signal\" to use Global clock" {  } { { "sld_rom_sr.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 36 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}