wuxian.fit.rpt

串口8位数据 verilog hdl提取

; Optimize Fast-Corner Timing                                           ; Off                            ; Off                            ;
; Equivalent RAM and MLAB Paused Read Capabilities                      ; Care                           ; Care                           ;
; PowerPlay Power Optimization                                          ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                       ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                            ; On                             ; On                             ;
; Limit to One Fitting Attempt                                          ; Off                            ; Off                            ;
; Final Placement Optimizations                                         ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                           ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                         ; 1                              ; 1                              ;
; PCI I/O                                                               ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                                 ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                             ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                    ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix II/II GX/III Cyclone II/III Arria GX ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                     ; On                             ; On                             ;
; Auto Merge PLLs                                                       ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs                                     ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Fitting        ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Performance    ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                          ; Off                            ; Off                            ;
; Perform Logic to Memory Mapping for Fitting                           ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                             ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                                ; Off                            ; Off                            ;
; Fitter Effort                                                         ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                       ; Normal                         ; Normal                         ;
; Auto Global Clock                                                     ; On                             ; On                             ;
; Auto Global Register Control Signals                                  ; On                             ; On                             ;
; Stop After Congestion Map Generation                                  ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                     ; Off                            ; Off                            ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in E:/workplace/wuxian/wuxian.pin.


+------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                          ;
+---------------------------------------------+--------------------------+
; Resource                                    ; Usage                    ;
+---------------------------------------------+--------------------------+
; Total logic elements                        ; 73 / 33,216 ( < 1 % )    ;
;     -- Combinational with no register       ; 27                       ;
;     -- Register only                        ; 8                        ;
;     -- Combinational with a register        ; 38                       ;
;                                             ;                          ;
; Logic element usage by number of LUT inputs ;                          ;
;     -- 4 input functions                    ; 16                       ;
;     -- 3 input functions                    ; 10                       ;
;     -- <=2 input functions                  ; 39                       ;
;     -- Register only                        ; 8                        ;
;                                             ;                          ;
; Logic elements by mode                      ;                          ;
;     -- normal mode                          ; 41                       ;
;     -- arithmetic mode                      ; 24                       ;
;                                             ;                          ;
; Total registers*                            ; 46 / 34,134 ( < 1 % )    ;
;     -- Dedicated logic registers            ; 46 / 33,216 ( < 1 % )    ;
;     -- I/O registers                        ; 0 / 918 ( 0 % )          ;
;                                             ;                          ;
; Total LABs:  partially or completely used   ; 6 / 2,076 ( < 1 % )      ;
; User inserted logic elements                ; 0                        ;
; Virtual pins                                ; 0                        ;
; I/O pins                                    ; 19 / 322 ( 6 % )         ;
;     -- Clock pins                           ; 1 / 8 ( 13 % )           ;
; Global signals                              ; 2                        ;
; M4Ks                                        ; 0 / 105 ( 0 % )          ;
; Total memory bits                           ; 0 / 483,840 ( 0 % )      ;
; Total RAM block bits                        ; 0 / 483,840 ( 0 % )      ;
; Embedded Multiplier 9-bit elements          ; 0 / 70 ( 0 % )           ;
; PLLs                                        ; 0 / 4 ( 0 % )            ;
; Global clocks                               ; 2 / 16 ( 13 % )          ;
; Average interconnect usage                  ; 0%                       ;
; Peak interconnect usage                     ; 0%                       ;
; Maximum fan-out node                        ; clock~clkctrl            ;
; Maximum fan-out                             ; 25                       ;
; Highest non-global fan-out signal           ; wuxian:inst|led_r[7]~290 ;
; Highest non-global fan-out                  ; 13                       ;
; Total fan-out                               ; 293                      ;
; Average fan-out                             ; 2.11                     ;
+---------------------------------------------+--------------------------+
*  Register count does not include registers inside RAM blocks or DSP blocks.



+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                  ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name  ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; clear ; R22   ; 6        ; 65           ; 13           ; 2           ; 13                    ; 0                  ; no     ; no             ; no            ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; User                 ;
; clock ; A12   ; 4        ; 31           ; 36           ; 1           ; 2                     ; 0                  ; yes    ; no             ; no            ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; User                 ;
; d     ; R21   ; 6        ; 65           ; 13           ; 3           ; 1                     ; 0                  ; no     ; no             ; no            ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; User                 ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+