wuxian.map.summary

来自「串口8位数据 verilog hdl提取」· SUMMARY 代码 · 共 15 行

Analysis & Synthesis Status : Successful - Fri May 22 09:01:43 2009
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : wuxian
Top-level Entity Name : wuxian_test
Family : Cyclone II
Total logic elements : 65
    Total combinational functions : 65
    Dedicated logic registers : 46
Total registers : 46
Total pins : 19
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0