wuxian.tan.qmsg

串口8位数据 verilog hdl提取

{ "Info" "ITDB_TH_RESULT" "wuxian:inst\|dout_r\[3\] clear clock 1.648 ns register " "Info: th for register \"wuxian:inst\|dout_r\[3\]\" (data pin = \"clear\", clock pin = \"clock\") is 1.648 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 8.382 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 8.382 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clock 1 CLK PIN_A12 2 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_A12; Fanout = 2; CLK Node = 'clock'" {  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "wuxian_test.bdf" "" { Schematic "E:/workplace/wuxian/wuxian_test.bdf" { { 152 16 184 168 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.032 ns) + CELL(0.970 ns) 4.092 ns int_div:inst1\|clk_temp1 2 REG LCFF_X34_Y21_N5 1 " "Info: 2: + IC(2.032 ns) + CELL(0.970 ns) = 4.092 ns; Loc. = LCFF_X34_Y21_N5; Fanout = 1; REG Node = 'int_div:inst1\|clk_temp1'" {  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.002 ns" { clock int_div:inst1|clk_temp1 } "NODE_NAME" } } { "int_div.v" "" { Text "E:/workplace/wuxian/int_div.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.458 ns) + CELL(0.000 ns) 6.550 ns int_div:inst1\|clk_temp1~clkctrl 3 COMB CLKCTRL_G9 20 " "Info: 3: + IC(2.458 ns) + CELL(0.000 ns) = 6.550 ns; Loc. = CLKCTRL_G9; Fanout = 20; COMB Node = 'int_div:inst1\|clk_temp1~clkctrl'" {  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.458 ns" { int_div:inst1|clk_temp1 int_div:inst1|clk_temp1~clkctrl } "NODE_NAME" } } { "int_div.v" "" { Text "E:/workplace/wuxian/int_div.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.166 ns) + CELL(0.666 ns) 8.382 ns wuxian:inst\|dout_r\[3\] 4 REG LCFF_X64_Y9_N17 3 " "Info: 4: + IC(1.166 ns) + CELL(0.666 ns) = 8.382 ns; Loc. = LCFF_X64_Y9_N17; Fanout = 3; REG Node = 'wuxian:inst\|dout_r\[3\]'" {  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.832 ns" { int_div:inst1|clk_temp1~clkctrl wuxian:inst|dout_r[3] } "NODE_NAME" } } { "wuxian.v" "" { Text "E:/workplace/wuxian/wuxian.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.726 ns ( 32.52 % ) " "Info: Total cell delay = 2.726 ns ( 32.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.656 ns ( 67.48 % ) " "Info: Total interconnect delay = 5.656 ns ( 67.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "8.382 ns" { clock int_div:inst1|clk_temp1 int_div:inst1|clk_temp1~clkctrl wuxian:inst|dout_r[3] } "NODE_NAME" } } { "e:/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus2/quartus/bin/Technology_Viewer.qrui" "8.382 ns" { clock {} clock~combout {} int_div:inst1|clk_temp1 {} int_div:inst1|clk_temp1~clkctrl {} wuxian:inst|dout_r[3] {} } { 0.000ns 0.000ns 2.032ns 2.458ns 1.166ns } { 0.000ns 1.090ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "wuxian.v" "" { Text "E:/workplace/wuxian/wuxian.v" 13 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.040 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.040 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.935 ns) 0.935 ns clear 1 PIN PIN_R22 13 " "Info: 1: + IC(0.000 ns) + CELL(0.935 ns) = 0.935 ns; Loc. = PIN_R22; Fanout = 13; PIN Node = 'clear'" {  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clear } "NODE_NAME" } } { "wuxian_test.bdf" "" { Schematic "E:/workplace/wuxian/wuxian_test.bdf" { { 136 320 488 152 "clear" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.795 ns) + CELL(0.202 ns) 6.932 ns wuxian:inst\|dout_r~292 2 COMB LCCOMB_X64_Y9_N16 1 " "Info: 2: + IC(5.795 ns) + CELL(0.202 ns) = 6.932 ns; Loc. = LCCOMB_X64_Y9_N16; Fanout = 1; COMB Node = 'wuxian:inst\|dout_r~292'" {  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "5.997 ns" { clear wuxian:inst|dout_r~292 } "NODE_NAME" } } { "wuxian.v" "" { Text "E:/workplace/wuxian/wuxian.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 7.040 ns wuxian:inst\|dout_r\[3\] 3 REG LCFF_X64_Y9_N17 3 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.040 ns; Loc. = LCFF_X64_Y9_N17; Fanout = 3; REG Node = 'wuxian:inst\|dout_r\[3\]'" {  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { wuxian:inst|dout_r~292 wuxian:inst|dout_r[3] } "NODE_NAME" } } { "wuxian.v" "" { Text "E:/workplace/wuxian/wuxian.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.245 ns ( 17.68 % ) " "Info: Total cell delay = 1.245 ns ( 17.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.795 ns ( 82.32 % ) " "Info: Total interconnect delay = 5.795 ns ( 82.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "7.040 ns" { clear wuxian:inst|dout_r~292 wuxian:inst|dout_r[3] } "NODE_NAME" } } { "e:/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus2/quartus/bin/Technology_Viewer.qrui" "7.040 ns" { clear {} clear~combout {} wuxian:inst|dout_r~292 {} wuxian:inst|dout_r[3] {} } { 0.000ns 0.000ns 5.795ns 0.000ns } { 0.000ns 0.935ns 0.202ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "8.382 ns" { clock int_div:inst1|clk_temp1 int_div:inst1|clk_temp1~clkctrl wuxian:inst|dout_r[3] } "NODE_NAME" } } { "e:/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus2/quartus/bin/Technology_Viewer.qrui" "8.382 ns" { clock {} clock~combout {} int_div:inst1|clk_temp1 {} int_div:inst1|clk_temp1~clkctrl {} wuxian:inst|dout_r[3] {} } { 0.000ns 0.000ns 2.032ns 2.458ns 1.166ns } { 0.000ns 1.090ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "7.040 ns" { clear wuxian:inst|dout_r~292 wuxian:inst|dout_r[3] } "NODE_NAME" } } { "e:/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus2/quartus/bin/Technology_Viewer.qrui" "7.040 ns" { clear {} clear~combout {} wuxian:inst|dout_r~292 {} wuxian:inst|dout_r[3] {} } { 0.000ns 0.000ns 5.795ns 0.000ns } { 0.000ns 0.935ns 0.202ns 0.108ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "119 " "Info: Allocated 119 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri May 22 09:02:08 2009 " "Info: Processing ended: Fri May 22 09:02:08 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}