wuxian.tan.qmsg

串口8位数据 verilog hdl提取

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "int_div:inst1\|clk_temp1 " "Info: Detected ripple clock \"int_div:inst1\|clk_temp1\" as buffer" {  } { { "int_div.v" "" { Text "E:/workplace/wuxian/int_div.v" 29 -1 0 } } { "e:/quartus2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus2/quartus/bin/Assignment Editor.qase" 1 { { 0 "int_div:inst1\|clk_temp1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register int_div:inst1\|counter1\[5\] register int_div:inst1\|counter1\[19\] 179.4 MHz 5.574 ns Internal " "Info: Clock \"clock\" has Internal fmax of 179.4 MHz between source register \"int_div:inst1\|counter1\[5\]\" and destination register \"int_div:inst1\|counter1\[19\]\" (period= 5.574 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.312 ns + Longest register register " "Info: + Longest register to register delay is 5.312 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int_div:inst1\|counter1\[5\] 1 REG LCFF_X35_Y22_N19 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X35_Y22_N19; Fanout = 3; REG Node = 'int_div:inst1\|counter1\[5\]'" {  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { int_div:inst1|counter1[5] } "NODE_NAME" } } { "int_div.v" "" { Text "E:/workplace/wuxian/int_div.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.116 ns) + CELL(0.614 ns) 1.730 ns int_div:inst1\|Equal0~273 2 COMB LCCOMB_X34_Y22_N14 1 " "Info: 2: + IC(1.116 ns) + CELL(0.614 ns) = 1.730 ns; Loc. = LCCOMB_X34_Y22_N14; Fanout = 1; COMB Node = 'int_div:inst1\|Equal0~273'" {  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.730 ns" { int_div:inst1|counter1[5] int_div:inst1|Equal0~273 } "NODE_NAME" } } { "int_div.v" "" { Text "E:/workplace/wuxian/int_div.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.674 ns) + CELL(0.206 ns) 2.610 ns int_div:inst1\|Equal0~275 3 COMB LCCOMB_X35_Y22_N0 1 " "Info: 3: + IC(0.674 ns) + CELL(0.206 ns) = 2.610 ns; Loc. = LCCOMB_X35_Y22_N0; Fanout = 1; COMB Node = 'int_div:inst1\|Equal0~275'" {  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "0.880 ns" { int_div:inst1|Equal0~273 int_div:inst1|Equal0~275 } "NODE_NAME" } } { "int_div.v" "" { Text "E:/workplace/wuxian/int_div.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.369 ns) + CELL(0.589 ns) 3.568 ns int_div:inst1\|Equal0~276 4 COMB LCCOMB_X35_Y22_N2 10 " "Info: 4: + IC(0.369 ns) + CELL(0.589 ns) = 3.568 ns; Loc. = LCCOMB_X35_Y22_N2; Fanout = 10; COMB Node = 'int_div:inst1\|Equal0~276'" {  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "0.958 ns" { int_div:inst1|Equal0~275 int_div:inst1|Equal0~276 } "NODE_NAME" } } { "int_div.v" "" { Text "E:/workplace/wuxian/int_div.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.434 ns) + CELL(0.202 ns) 5.204 ns int_div:inst1\|counter1~247 5 COMB LCCOMB_X34_Y21_N12 1 " "Info: 5: + IC(1.434 ns) + CELL(0.202 ns) = 5.204 ns; Loc. = LCCOMB_X34_Y21_N12; Fanout = 1; COMB Node = 'int_div:inst1\|counter1~247'" {  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.636 ns" { int_div:inst1|Equal0~276 int_div:inst1|counter1~247 } "NODE_NAME" } } { "int_div.v" "" { Text "E:/workplace/wuxian/int_div.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 5.312 ns int_div:inst1\|counter1\[19\] 6 REG LCFF_X34_Y21_N13 4 " "Info: 6: + IC(0.000 ns) + CELL(0.108 ns) = 5.312 ns; Loc. = LCFF_X34_Y21_N13; Fanout = 4; REG Node = 'int_div:inst1\|counter1\[19\]'" {  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { int_div:inst1|counter1~247 int_div:inst1|counter1[19] } "NODE_NAME" } } { "int_div.v" "" { Text "E:/workplace/wuxian/int_div.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.719 ns ( 32.36 % ) " "Info: Total cell delay = 1.719 ns ( 32.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.593 ns ( 67.64 % ) " "Info: Total interconnect delay = 3.593 ns ( 67.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "5.312 ns" { int_div:inst1|counter1[5] int_div:inst1|Equal0~273 int_div:inst1|Equal0~275 int_div:inst1|Equal0~276 int_div:inst1|counter1~247 int_div:inst1|counter1[19] } "NODE_NAME" } } { "e:/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus2/quartus/bin/Technology_Viewer.qrui" "5.312 ns" { int_div:inst1|counter1[5] {} int_div:inst1|Equal0~273 {} int_div:inst1|Equal0~275 {} int_div:inst1|Equal0~276 {} int_div:inst1|counter1~247 {} int_div:inst1|counter1[19] {} } { 0.000ns 1.116ns 0.674ns 0.369ns 1.434ns 0.000ns } { 0.000ns 0.614ns 0.206ns 0.589ns 0.202ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.002 ns - Smallest " "Info: - Smallest clock skew is 0.002 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 3.161 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 3.161 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clock 1 CLK PIN_A12 2 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_A12; Fanout = 2; CLK Node = 'clock'" {  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "wuxian_test.bdf" "" { Schematic "E:/workplace/wuxian/wuxian_test.bdf" { { 152 16 184 168 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.232 ns) + CELL(0.000 ns) 1.322 ns clock~clkctrl 2 COMB CLKCTRL_G10 25 " "Info: 2: + IC(0.232 ns) + CELL(0.000 ns) = 1.322 ns; Loc. = CLKCTRL_G10; Fanout = 25; COMB Node = 'clock~clkctrl'" {  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "0.232 ns" { clock clock~clkctrl } "NODE_NAME" } } { "wuxian_test.bdf" "" { Schematic "E:/workplace/wuxian/wuxian_test.bdf" { { 152 16 184 168 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.173 ns) + CELL(0.666 ns) 3.161 ns int_div:inst1\|counter1\[19\] 3 REG LCFF_X34_Y21_N13 4 " "Info: 3: + IC(1.173 ns) + CELL(0.666 ns) = 3.161 ns; Loc. = LCFF_X34_Y21_N13; Fanout = 4; REG Node = 'int_div:inst1\|counter1\[19\]'" {  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.839 ns" { clock~clkctrl int_div:inst1|counter1[19] } "NODE_NAME" } } { "int_div.v" "" { Text "E:/workplace/wuxian/int_div.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 55.55 % ) " "Info: Total cell delay = 1.756 ns ( 55.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.405 ns ( 44.45 % ) " "Info: Total interconnect delay = 1.405 ns ( 44.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.161 ns" { clock clock~clkctrl int_div:inst1|counter1[19] } "NODE_NAME" } } { "e:/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus2/quartus/bin/Technology_Viewer.qrui" "3.161 ns" { clock {} clock~combout {} clock~clkctrl {} int_div:inst1|counter1[19] {} } { 0.000ns 0.000ns 0.232ns 1.173ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 3.159 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 3.159 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clock 1 CLK PIN_A12 2 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_A12; Fanout = 2; CLK Node = 'clock'" {  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "wuxian_test.bdf" "" { Schematic "E:/workplace/wuxian/wuxian_test.bdf" { { 152 16 184 168 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.232 ns) + CELL(0.000 ns) 1.322 ns clock~clkctrl 2 COMB CLKCTRL_G10 25 " "Info: 2: + IC(0.232 ns) + CELL(0.000 ns) = 1.322 ns; Loc. = CLKCTRL_G10; Fanout = 25; COMB Node = 'clock~clkctrl'" {  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "0.232 ns" { clock clock~clkctrl } "NODE_NAME" } } { "wuxian_test.bdf" "" { Schematic "E:/workplace/wuxian/wuxian_test.bdf" { { 152 16 184 168 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.171 ns) + CELL(0.666 ns) 3.159 ns int_div:inst1\|counter1\[5\] 3 REG LCFF_X35_Y22_N19 3 " "Info: 3: + IC(1.171 ns) + CELL(0.666 ns) = 3.159 ns; Loc. = LCFF_X35_Y22_N19; Fanout = 3; REG Node = 'int_div:inst1\|counter1\[5\]'" {  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.837 ns" { clock~clkctrl int_div:inst1|counter1[5] } "NODE_NAME" } } { "int_div.v" "" { Text "E:/workplace/wuxian/int_div.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 55.59 % ) " "Info: Total cell delay = 1.756 ns ( 55.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.403 ns ( 44.41 % ) " "Info: Total interconnect delay = 1.403 ns ( 44.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.159 ns" { clock clock~clkctrl int_div:inst1|counter1[5] } "NODE_NAME" } } { "e:/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus2/quartus/bin/Technology_Viewer.qrui" "3.159 ns" { clock {} clock~combout {} clock~clkctrl {} int_div:inst1|counter1[5] {} } { 0.000ns 0.000ns 0.232ns 1.171ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.161 ns" { clock clock~clkctrl int_div:inst1|counter1[19] } "NODE_NAME" } } { "e:/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus2/quartus/bin/Technology_Viewer.qrui" "3.161 ns" { clock {} clock~combout {} clock~clkctrl {} int_div:inst1|counter1[19] {} } { 0.000ns 0.000ns 0.232ns 1.173ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.159 ns" { clock clock~clkctrl int_div:inst1|counter1[5] } "NODE_NAME" } } { "e:/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus2/quartus/bin/Technology_Viewer.qrui" "3.159 ns" { clock {} clock~combout {} clock~clkctrl {} int_div:inst1|counter1[5] {} } { 0.000ns 0.000ns 0.232ns 1.171ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "int_div.v" "" { Text "E:/workplace/wuxian/int_div.v" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "int_div.v" "" { Text "E:/workplace/wuxian/int_div.v" 19 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "5.312 ns" { int_div:inst1|counter1[5] int_div:inst1|Equal0~273 int_div:inst1|Equal0~275 int_div:inst1|Equal0~276 int_div:inst1|counter1~247 int_div:inst1|counter1[19] } "NODE_NAME" } } { "e:/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus2/quartus/bin/Technology_Viewer.qrui" "5.312 ns" { int_div:inst1|counter1[5] {} int_div:inst1|Equal0~273 {} int_div:inst1|Equal0~275 {} int_div:inst1|Equal0~276 {} int_div:inst1|counter1~247 {} int_div:inst1|counter1[19] {} } { 0.000ns 1.116ns 0.674ns 0.369ns 1.434ns 0.000ns } { 0.000ns 0.614ns 0.206ns 0.589ns 0.202ns 0.108ns } "" } } { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.161 ns" { clock clock~clkctrl int_div:inst1|counter1[19] } "NODE_NAME" } } { "e:/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus2/quartus/bin/Technology_Viewer.qrui" "3.161 ns" { clock {} clock~combout {} clock~clkctrl {} int_div:inst1|counter1[19] {} } { 0.000ns 0.000ns 0.232ns 1.173ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.159 ns" { clock clock~clkctrl int_div:inst1|counter1[5] } "NODE_NAME" } } { "e:/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus2/quartus/bin/Technology_Viewer.qrui" "3.159 ns" { clock {} clock~combout {} clock~clkctrl {} int_div:inst1|counter1[5] {} } { 0.000ns 0.000ns 0.232ns 1.171ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "wuxian:inst\|led_r\[7\] clear clock 0.687 ns register " "Info: tsu for register \"wuxian:inst\|led_r\[7\]\" (data pin = \"clear\", clock pin = \"clock\") is 0.687 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.133 ns + Longest pin register " "Info: + Longest pin to register delay is 9.133 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.935 ns) 0.935 ns clear 1 PIN PIN_R22 13 " "Info: 1: + IC(0.000 ns) + CELL(0.935 ns) = 0.935 ns; Loc. = PIN_R22; Fanout = 13; PIN Node = 'clear'" {  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clear } "NODE_NAME" } } { "wuxian_test.bdf" "" { Schematic "E:/workplace/wuxian/wuxian_test.bdf" { { 136 320 488 152 "clear" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.806 ns) + CELL(0.505 ns) 7.246 ns wuxian:inst\|led_r\[7\]~291 2 COMB LCCOMB_X64_Y9_N24 8 " "Info: 2: + IC(5.806 ns) + CELL(0.505 ns) = 7.246 ns; Loc. = LCCOMB_X64_Y9_N24; Fanout = 8; COMB Node = 'wuxian:inst\|led_r\[7\]~291'" {  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "6.311 ns" { clear wuxian:inst|led_r[7]~291 } "NODE_NAME" } } { "wuxian.v" "" { Text "E:/workplace/wuxian/wuxian.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.032 ns) + CELL(0.855 ns) 9.133 ns wuxian:inst\|led_r\[7\] 3 REG LCFF_X64_Y6_N1 1 " "Info: 3: + IC(1.032 ns) + CELL(0.855 ns) = 9.133 ns; Loc. = LCFF_X64_Y6_N1; Fanout = 1; REG Node = 'wuxian:inst\|led_r\[7\]'" {  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.887 ns" { wuxian:inst|led_r[7]~291 wuxian:inst|led_r[7] } "NODE_NAME" } } { "wuxian.v" "" { Text "E:/workplace/wuxian/wuxian.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.295 ns ( 25.13 % ) " "Info: Total cell delay = 2.295 ns ( 25.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.838 ns ( 74.87 % ) " "Info: Total interconnect delay = 6.838 ns ( 74.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "9.133 ns" { clear wuxian:inst|led_r[7]~291 wuxian:inst|led_r[7] } "NODE_NAME" } } { "e:/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus2/quartus/bin/Technology_Viewer.qrui" "9.133 ns" { clear {} clear~combout {} wuxian:inst|led_r[7]~291 {} wuxian:inst|led_r[7] {} } { 0.000ns 0.000ns 5.806ns 1.032ns } { 0.000ns 0.935ns 0.505ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "wuxian.v" "" { Text "E:/workplace/wuxian/wuxian.v" 13 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 8.406 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 8.406 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clock 1 CLK PIN_A12 2 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_A12; Fanout = 2; CLK Node = 'clock'" {  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "wuxian_test.bdf" "" { Schematic "E:/workplace/wuxian/wuxian_test.bdf" { { 152 16 184 168 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.032 ns) + CELL(0.970 ns) 4.092 ns int_div:inst1\|clk_temp1 2 REG LCFF_X34_Y21_N5 1 " "Info: 2: + IC(2.032 ns) + CELL(0.970 ns) = 4.092 ns; Loc. = LCFF_X34_Y21_N5; Fanout = 1; REG Node = 'int_div:inst1\|clk_temp1'" {  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.002 ns" { clock int_div:inst1|clk_temp1 } "NODE_NAME" } } { "int_div.v" "" { Text "E:/workplace/wuxian/int_div.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.458 ns) + CELL(0.000 ns) 6.550 ns int_div:inst1\|clk_temp1~clkctrl 3 COMB CLKCTRL_G9 20 " "Info: 3: + IC(2.458 ns) + CELL(0.000 ns) = 6.550 ns; Loc. = CLKCTRL_G9; Fanout = 20; COMB Node = 'int_div:inst1\|clk_temp1~clkctrl'" {  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.458 ns" { int_div:inst1|clk_temp1 int_div:inst1|clk_temp1~clkctrl } "NODE_NAME" } } { "int_div.v" "" { Text "E:/workplace/wuxian/int_div.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.190 ns) + CELL(0.666 ns) 8.406 ns wuxian:inst\|led_r\[7\] 4 REG LCFF_X64_Y6_N1 1 " "Info: 4: + IC(1.190 ns) + CELL(0.666 ns) = 8.406 ns; Loc. = LCFF_X64_Y6_N1; Fanout = 1; REG Node = 'wuxian:inst\|led_r\[7\]'" {  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.856 ns" { int_div:inst1|clk_temp1~clkctrl wuxian:inst|led_r[7] } "NODE_NAME" } } { "wuxian.v" "" { Text "E:/workplace/wuxian/wuxian.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.726 ns ( 32.43 % ) " "Info: Total cell delay = 2.726 ns ( 32.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.680 ns ( 67.57 % ) " "Info: Total interconnect delay = 5.680 ns ( 67.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "8.406 ns" { clock int_div:inst1|clk_temp1 int_div:inst1|clk_temp1~clkctrl wuxian:inst|led_r[7] } "NODE_NAME" } } { "e:/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus2/quartus/bin/Technology_Viewer.qrui" "8.406 ns" { clock {} clock~combout {} int_div:inst1|clk_temp1 {} int_div:inst1|clk_temp1~clkctrl {} wuxian:inst|led_r[7] {} } { 0.000ns 0.000ns 2.032ns 2.458ns 1.190ns } { 0.000ns 1.090ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "9.133 ns" { clear wuxian:inst|led_r[7]~291 wuxian:inst|led_r[7] } "NODE_NAME" } } { "e:/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus2/quartus/bin/Technology_Viewer.qrui" "9.133 ns" { clear {} clear~combout {} wuxian:inst|led_r[7]~291 {} wuxian:inst|led_r[7] {} } { 0.000ns 0.000ns 5.806ns 1.032ns } { 0.000ns 0.935ns 0.505ns 0.855ns } "" } } { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "8.406 ns" { clock int_div:inst1|clk_temp1 int_div:inst1|clk_temp1~clkctrl wuxian:inst|led_r[7] } "NODE_NAME" } } { "e:/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus2/quartus/bin/Technology_Viewer.qrui" "8.406 ns" { clock {} clock~combout {} int_div:inst1|clk_temp1 {} int_div:inst1|clk_temp1~clkctrl {} wuxian:inst|led_r[7] {} } { 0.000ns 0.000ns 2.032ns 2.458ns 1.190ns } { 0.000ns 1.090ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock dout\[1\] wuxian:inst\|dout_r\[1\] 13.180 ns register " "Info: tco from clock \"clock\" to destination pin \"dout\[1\]\" through register \"wuxian:inst\|dout_r\[1\]\" is 13.180 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 8.382 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 8.382 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clock 1 CLK PIN_A12 2 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_A12; Fanout = 2; CLK Node = 'clock'" {  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "wuxian_test.bdf" "" { Schematic "E:/workplace/wuxian/wuxian_test.bdf" { { 152 16 184 168 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.032 ns) + CELL(0.970 ns) 4.092 ns int_div:inst1\|clk_temp1 2 REG LCFF_X34_Y21_N5 1 " "Info: 2: + IC(2.032 ns) + CELL(0.970 ns) = 4.092 ns; Loc. = LCFF_X34_Y21_N5; Fanout = 1; REG Node = 'int_div:inst1\|clk_temp1'" {  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.002 ns" { clock int_div:inst1|clk_temp1 } "NODE_NAME" } } { "int_div.v" "" { Text "E:/workplace/wuxian/int_div.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.458 ns) + CELL(0.000 ns) 6.550 ns int_div:inst1\|clk_temp1~clkctrl 3 COMB CLKCTRL_G9 20 " "Info: 3: + IC(2.458 ns) + CELL(0.000 ns) = 6.550 ns; Loc. = CLKCTRL_G9; Fanout = 20; COMB Node = 'int_div:inst1\|clk_temp1~clkctrl'" {  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.458 ns" { int_div:inst1|clk_temp1 int_div:inst1|clk_temp1~clkctrl } "NODE_NAME" } } { "int_div.v" "" { Text "E:/workplace/wuxian/int_div.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.166 ns) + CELL(0.666 ns) 8.382 ns wuxian:inst\|dout_r\[1\] 4 REG LCFF_X64_Y9_N23 3 " "Info: 4: + IC(1.166 ns) + CELL(0.666 ns) = 8.382 ns; Loc. = LCFF_X64_Y9_N23; Fanout = 3; REG Node = 'wuxian:inst\|dout_r\[1\]'" {  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.832 ns" { int_div:inst1|clk_temp1~clkctrl wuxian:inst|dout_r[1] } "NODE_NAME" } } { "wuxian.v" "" { Text "E:/workplace/wuxian/wuxian.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.726 ns ( 32.52 % ) " "Info: Total cell delay = 2.726 ns ( 32.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.656 ns ( 67.48 % ) " "Info: Total interconnect delay = 5.656 ns ( 67.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "8.382 ns" { clock int_div:inst1|clk_temp1 int_div:inst1|clk_temp1~clkctrl wuxian:inst|dout_r[1] } "NODE_NAME" } } { "e:/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus2/quartus/bin/Technology_Viewer.qrui" "8.382 ns" { clock {} clock~combout {} int_div:inst1|clk_temp1 {} int_div:inst1|clk_temp1~clkctrl {} wuxian:inst|dout_r[1] {} } { 0.000ns 0.000ns 2.032ns 2.458ns 1.166ns } { 0.000ns 1.090ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "wuxian.v" "" { Text "E:/workplace/wuxian/wuxian.v" 13 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.494 ns + Longest register pin " "Info: + Longest register to pin delay is 4.494 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns wuxian:inst\|dout_r\[1\] 1 REG LCFF_X64_Y9_N23 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X64_Y9_N23; Fanout = 3; REG Node = 'wuxian:inst\|dout_r\[1\]'" {  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { wuxian:inst|dout_r[1] } "NODE_NAME" } } { "wuxian.v" "" { Text "E:/workplace/wuxian/wuxian.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.428 ns) + CELL(3.066 ns) 4.494 ns dout\[1\] 2 PIN PIN_Y22 0 " "Info: 2: + IC(1.428 ns) + CELL(3.066 ns) = 4.494 ns; Loc. = PIN_Y22; Fanout = 0; PIN Node = 'dout\[1\]'" {  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "4.494 ns" { wuxian:inst|dout_r[1] dout[1] } "NODE_NAME" } } { "wuxian_test.bdf" "" { Schematic "E:/workplace/wuxian/wuxian_test.bdf" { { 80 776 952 96 "dout\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.066 ns ( 68.22 % ) " "Info: Total cell delay = 3.066 ns ( 68.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.428 ns ( 31.78 % ) " "Info: Total interconnect delay = 1.428 ns ( 31.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "4.494 ns" { wuxian:inst|dout_r[1] dout[1] } "NODE_NAME" } } { "e:/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus2/quartus/bin/Technology_Viewer.qrui" "4.494 ns" { wuxian:inst|dout_r[1] {} dout[1] {} } { 0.000ns 1.428ns } { 0.000ns 3.066ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "8.382 ns" { clock int_div:inst1|clk_temp1 int_div:inst1|clk_temp1~clkctrl wuxian:inst|dout_r[1] } "NODE_NAME" } } { "e:/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus2/quartus/bin/Technology_Viewer.qrui" "8.382 ns" { clock {} clock~combout {} int_div:inst1|clk_temp1 {} int_div:inst1|clk_temp1~clkctrl {} wuxian:inst|dout_r[1] {} } { 0.000ns 0.000ns 2.032ns 2.458ns 1.166ns } { 0.000ns 1.090ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "4.494 ns" { wuxian:inst|dout_r[1] dout[1] } "NODE_NAME" } } { "e:/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus2/quartus/bin/Technology_Viewer.qrui" "4.494 ns" { wuxian:inst|dout_r[1] {} dout[1] {} } { 0.000ns 1.428ns } { 0.000ns 3.066ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}