wuxian.hier_info

串口8位数据 verilog hdl提取

|wuxian_test
dout[0] <= wuxian:inst.dout[0]
dout[1] <= wuxian:inst.dout[1]
dout[2] <= wuxian:inst.dout[2]
dout[3] <= wuxian:inst.dout[3]
dout[4] <= wuxian:inst.dout[4]
dout[5] <= wuxian:inst.dout[5]
dout[6] <= wuxian:inst.dout[6]
dout[7] <= wuxian:inst.dout[7]
d => wuxian:inst.d
clear => wuxian:inst.clear
clock => int_div:inst1.clk_in
led[0] <= wuxian:inst.led[0]
led[1] <= wuxian:inst.led[1]
led[2] <= wuxian:inst.led[2]
led[3] <= wuxian:inst.led[3]
led[4] <= wuxian:inst.led[4]
led[5] <= wuxian:inst.led[5]
led[6] <= wuxian:inst.led[6]
led[7] <= wuxian:inst.led[7]


|wuxian_test|wuxian:inst
d => dout_r~7.DATAA
clear => add~7.OUTPUTSELECT
clear => add~6.OUTPUTSELECT
clear => add~5.OUTPUTSELECT
clear => add~4.OUTPUTSELECT
clear => dout_r~15.OUTPUTSELECT
clear => dout_r~14.OUTPUTSELECT
clear => dout_r~13.OUTPUTSELECT
clear => dout_r~12.OUTPUTSELECT
clear => dout_r~11.OUTPUTSELECT
clear => dout_r~10.OUTPUTSELECT
clear => dout_r~9.OUTPUTSELECT
clear => dout_r~8.OUTPUTSELECT
clear => led_r[1].ENA
clear => led_r[0].ENA
clear => led_r[2].ENA
clear => led_r[3].ENA
clear => led_r[4].ENA
clear => led_r[5].ENA
clear => led_r[6].ENA
clear => led_r[7].ENA
dout[0] <= dout_r[0].DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= dout_r[1].DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= dout_r[2].DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= dout_r[3].DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= dout_r[4].DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= dout_r[5].DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= dout_r[6].DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= dout_r[7].DB_MAX_OUTPUT_PORT_TYPE
clk => dout_r[7].CLK
clk => dout_r[6].CLK
clk => dout_r[5].CLK
clk => dout_r[4].CLK
clk => dout_r[3].CLK
clk => dout_r[2].CLK
clk => dout_r[1].CLK
clk => dout_r[0].CLK
clk => add[3].CLK
clk => add[2].CLK
clk => add[1].CLK
clk => add[0].CLK
clk => led_r[7].CLK
clk => led_r[6].CLK
clk => led_r[5].CLK
clk => led_r[4].CLK
clk => led_r[3].CLK
clk => led_r[2].CLK
clk => led_r[1].CLK
clk => led_r[0].CLK
led[0] <= led_r[0].DB_MAX_OUTPUT_PORT_TYPE
led[1] <= led_r[1].DB_MAX_OUTPUT_PORT_TYPE
led[2] <= led_r[2].DB_MAX_OUTPUT_PORT_TYPE
led[3] <= led_r[3].DB_MAX_OUTPUT_PORT_TYPE
led[4] <= led_r[4].DB_MAX_OUTPUT_PORT_TYPE
led[5] <= led_r[5].DB_MAX_OUTPUT_PORT_TYPE
led[6] <= led_r[6].DB_MAX_OUTPUT_PORT_TYPE
led[7] <= led_r[7].DB_MAX_OUTPUT_PORT_TYPE


|wuxian_test|int_div:inst1
clk_in => counter1[24].CLK
clk_in => counter1[23].CLK
clk_in => counter1[22].CLK
clk_in => counter1[21].CLK
clk_in => counter1[20].CLK
clk_in => counter1[19].CLK
clk_in => counter1[18].CLK
clk_in => counter1[17].CLK
clk_in => counter1[16].CLK
clk_in => counter1[15].CLK
clk_in => counter1[14].CLK
clk_in => counter1[13].CLK
clk_in => counter1[12].CLK
clk_in => counter1[11].CLK
clk_in => counter1[10].CLK
clk_in => counter1[9].CLK
clk_in => counter1[8].CLK
clk_in => counter1[7].CLK
clk_in => counter1[6].CLK
clk_in => counter1[5].CLK
clk_in => counter1[4].CLK
clk_in => counter1[3].CLK
clk_in => counter1[2].CLK
clk_in => counter1[1].CLK
clk_in => counter1[0].CLK
clk_in => clk_temp1.CLK
clk_out <= clk_temp1.DB_MAX_OUTPUT_PORT_TYPE