int_div.v

来自「串口8位数据 verilog hdl提取」· Verilog 代码 · 共 69 行

module int_div(clk_in,clk_out);

input clk_in;
output clk_out;

reg[div_width-1:0] counter1;
reg[div_width-1:0] counter2;
reg[div_width-1:0] counter3;

reg clk_temp1;
reg clk_temp2;
reg clk_temp3;

parameter diver=24000000;
parameter div_width=25;

assign clk_out=(diver%2==0)? clk_temp1:(clk_temp2|clk_temp3);

always@(posedge clk_in)
begin
	if(counter1==diver-1)
		counter1<=0;
	else
	begin
		counter1<=counter1+1'b1;
	end
end

always@(posedge clk_in)
begin
	if(counter1<=(diver/2)-1)
		clk_temp1<=1'b1;
	else
		clk_temp1<=1'b0;
end

always@(posedge clk_in)
begin
	if(counter2==diver-1)
		counter2<=0;
	else
		counter2<=counter2+1'b1;
end

always@(posedge clk_in)
begin
	if(counter2<(diver-1)/2)
		clk_temp2<=1'b1;
	else
		clk_temp2<=1'b0;
end

always@(negedge clk_in)
begin
	if(counter3==diver-1)
		counter3<=0;
	else
		counter3<=counter3+1'b1;
end

always@(negedge clk_in)
begin
	if(counter3<(diver-1)/2)
		clk_temp3<=1'b1;
	else
		clk_temp3<=1'b0;
end

endmodule