demux4.tan.rpt

这是个四输入乘法器

Classic Timing Analyzer report for demux4
Tue Oct 14 15:59:21 2008
Quartus II Version 6.1 Build 201 11/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                 ;
+------------------------------+-------+---------------+-------------+--------+----+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From   ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+--------+----+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 9.413 ns    ; sel[0] ; b  ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;        ;    ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+--------+----+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C35F672C6       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-----------------------------------------------------------+
; tpd                                                       ;
+-------+-------------------+-----------------+--------+----+
; Slack ; Required P2P Time ; Actual P2P Time ; From   ; To ;
+-------+-------------------+-----------------+--------+----+
; N/A   ; None              ; 9.413 ns        ; sel[0] ; b  ;
; N/A   ; None              ; 9.408 ns        ; sel[0] ; a  ;
; N/A   ; None              ; 9.209 ns        ; sel[0] ; c  ;
; N/A   ; None              ; 9.194 ns        ; sel[0] ; d  ;
; N/A   ; None              ; 5.878 ns        ; sel[1] ; b  ;
; N/A   ; None              ; 5.874 ns        ; sel[1] ; a  ;
; N/A   ; None              ; 5.733 ns        ; q      ; b  ;
; N/A   ; None              ; 5.725 ns        ; q      ; a  ;
; N/A   ; None              ; 5.717 ns        ; sel[1] ; c  ;
; N/A   ; None              ; 5.683 ns        ; sel[1] ; d  ;
; N/A   ; None              ; 5.534 ns        ; q      ; c  ;
; N/A   ; None              ; 5.525 ns        ; q      ; d  ;
+-------+-------------------+-----------------+--------+----+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Tue Oct 14 15:59:21 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off demux4 -c demux4 --timing_analysis_only
Info: Longest tpd from source pin "sel[0]" to destination pin "b" is 9.413 ns
    Info: 1: + IC(0.000 ns) + CELL(0.840 ns) = 0.840 ns; Loc. = PIN_C12; Fanout = 4; PIN Node = 'sel[0]'
    Info: 2: + IC(4.824 ns) + CELL(0.150 ns) = 5.814 ns; Loc. = LCCOMB_X28_Y35_N4; Fanout = 1; COMB Node = 'b~9'
    Info: 3: + IC(0.821 ns) + CELL(2.778 ns) = 9.413 ns; Loc. = PIN_J13; Fanout = 0; PIN Node = 'b'
    Info: Total cell delay = 3.768 ns ( 40.03 % )
    Info: Total interconnect delay = 5.645 ns ( 59.97 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Allocated 103 megabytes of memory during processing
    Info: Processing ended: Tue Oct 14 15:59:21 2008
    Info: Elapsed time: 00:00:00