topmod.tan.rpt

这是个128位的串行伪随机码发生器

; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; divider3:inst|inst  ; divider3:inst|inst1 ; clk        ; clk      ; None                        ; None                      ; 0.533 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; pn127:inst1|inst6   ; pn127:inst1|inst    ; clk        ; clk      ; None                        ; None                      ; 0.822 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; divider3:inst|inst  ; divider3:inst|inst  ; clk        ; clk      ; None                        ; None                      ; 0.929 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; pn127:inst1|inst5   ; pn127:inst1|inst6   ; clk        ; clk      ; None                        ; None                      ; 0.690 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; pn127:inst1|inst1   ; pn127:inst1|inst2   ; clk        ; clk      ; None                        ; None                      ; 0.688 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; pn127:inst1|inst3   ; pn127:inst1|inst4   ; clk        ; clk      ; None                        ; None                      ; 0.686 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; pn127:inst1|inst5   ; pn127:inst1|inst    ; clk        ; clk      ; None                        ; None                      ; 0.682 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; pn127:inst1|inst2   ; pn127:inst1|inst3   ; clk        ; clk      ; None                        ; None                      ; 0.676 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; pn127:inst1|inst    ; pn127:inst1|inst1   ; clk        ; clk      ; None                        ; None                      ; 0.543 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; pn127:inst1|inst4   ; pn127:inst1|inst5   ; clk        ; clk      ; None                        ; None                      ; 0.537 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; divider3:inst|inst2 ; divider3:inst|inst2 ; clk        ; clk      ; None                        ; None                      ; 0.407 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; divider3:inst|inst1 ; divider3:inst|inst1 ; clk        ; clk      ; None                        ; None                      ; 0.407 ns                ;
+-------+------------------------------------------------+---------------------+---------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+----------------------------------------------------------------------------+
; tco                                                                        ;
+-------+--------------+------------+-------------------+-------+------------+
; Slack ; Required tco ; Actual tco ; From              ; To    ; From Clock ;
+-------+--------------+------------+-------------------+-------+------------+
; N/A   ; None         ; 10.669 ns  ; pn127:inst1|inst6 ; pn127 ; clk        ;
+-------+--------------+------------+-------------------+-------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Tue Sep 23 16:30:59 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off topmod -c topmod --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "divider3:inst|inst" as buffer
    Info: Detected ripple clock "divider3:inst|inst1" as buffer
    Info: Detected gated clock "divider3:inst|inst5" as buffer
    Info: Detected ripple clock "divider3:inst|inst2" as buffer
Info: Clock "clk" Internal fmax is restricted to 420.17 MHz between source register "divider3:inst|inst1" and destination register "divider3:inst|inst"
    Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.803 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X63_Y23_N31; Fanout = 1; REG Node = 'divider3:inst|inst1'
            Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X63_Y23_N30; Fanout = 3; COMB Node = 'divider3:inst|inst5'
            Info: 3: + IC(0.247 ns) + CELL(0.149 ns) = 0.719 ns; Loc. = LCCOMB_X63_Y23_N0; Fanout = 1; COMB Node = 'divider3:inst|inst~feeder'
            Info: 4: + IC(0.000 ns) + CELL(0.084 ns) = 0.803 ns; Loc. = LCFF_X63_Y23_N1; Fanout = 1; REG Node = 'divider3:inst|inst'
            Info: Total cell delay = 0.556 ns ( 69.24 % )
            Info: Total interconnect delay = 0.247 ns ( 30.76 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.678 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 2; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(1.024 ns) + CELL(0.537 ns) = 2.678 ns; Loc. = LCFF_X63_Y23_N1; Fanout = 1; REG Node = 'divider3:inst|inst'
                Info: Total cell delay = 1.536 ns ( 57.36 % )
                Info: Total interconnect delay = 1.142 ns ( 42.64 % )
            Info: - Longest clock path from clock "clk" to source register is 2.678 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 2; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(1.024 ns) + CELL(0.537 ns) = 2.678 ns; Loc. = LCFF_X63_Y23_N31; Fanout = 1; REG Node = 'divider3:inst|inst1'
                Info: Total cell delay = 1.536 ns ( 57.36 % )
                Info: Total interconnect delay = 1.142 ns ( 42.64 % )
        Info: + Micro clock to output delay of source is 0.250 ns
        Info: + Micro setup delay of destination is -0.036 ns
        Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two
Info: tco from clock "clk" to destination pin "pn127" through register "pn127:inst1|inst6" is 10.669 ns
    Info: + Longest clock path from clock "clk" to source register is 7.011 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 2; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.024 ns) + CELL(0.787 ns) = 2.928 ns; Loc. = LCFF_X63_Y23_N1; Fanout = 1; REG Node = 'divider3:inst|inst'
        Info: 4: + IC(0.299 ns) + CELL(0.150 ns) = 3.377 ns; Loc. = LCCOMB_X63_Y23_N30; Fanout = 3; COMB Node = 'divider3:inst|inst5'
        Info: 5: + IC(0.371 ns) + CELL(0.787 ns) = 4.535 ns; Loc. = LCFF_X64_Y23_N31; Fanout = 2; REG Node = 'divider3:inst|inst2'
        Info: 6: + IC(0.892 ns) + CELL(0.000 ns) = 5.427 ns; Loc. = CLKCTRL_G5; Fanout = 7; COMB Node = 'divider3:inst|inst2~clkctrl'
        Info: 7: + IC(1.047 ns) + CELL(0.537 ns) = 7.011 ns; Loc. = LCFF_X25_Y35_N19; Fanout = 3; REG Node = 'pn127:inst1|inst6'
        Info: Total cell delay = 3.260 ns ( 46.50 % )
        Info: Total interconnect delay = 3.751 ns ( 53.50 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 3.408 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X25_Y35_N19; Fanout = 3; REG Node = 'pn127:inst1|inst6'
        Info: 2: + IC(0.630 ns) + CELL(2.778 ns) = 3.408 ns; Loc. = PIN_J14; Fanout = 0; PIN Node = 'pn127'
        Info: Total cell delay = 2.778 ns ( 81.51 % )
        Info: Total interconnect delay = 0.630 ns ( 18.49 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Allocated 103 megabytes of memory during processing
    Info: Processing ended: Tue Sep 23 16:30:59 2008
    Info: Elapsed time: 00:00:00