divider3.tan.qmsg

这是个128位的串行伪随机码发生器

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register inst1 inst 420.17 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 420.17 MHz between source register \"inst1\" and destination register \"inst\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.38 ns " "Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.803 ns + Longest register register " "Info: + Longest register to register delay is 0.803 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inst1 1 REG LCFF_X63_Y20_N31 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X63_Y20_N31; Fanout = 1; REG Node = 'inst1'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { inst1 } "NODE_NAME" } } { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 216 264 328 296 "inst1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.323 ns) 0.323 ns inst5 2 COMB LCCOMB_X63_Y20_N30 3 " "Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X63_Y20_N30; Fanout = 3; COMB Node = 'inst5'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.323 ns" { inst1 inst5 } "NODE_NAME" } } { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 160 352 416 208 "inst5" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.247 ns) + CELL(0.149 ns) 0.719 ns inst~feeder 3 COMB LCCOMB_X63_Y20_N0 1 " "Info: 3: + IC(0.247 ns) + CELL(0.149 ns) = 0.719 ns; Loc. = LCCOMB_X63_Y20_N0; Fanout = 1; COMB Node = 'inst~feeder'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.396 ns" { inst5 inst~feeder } "NODE_NAME" } } { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 104 264 328 184 "inst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.803 ns inst 4 REG LCFF_X63_Y20_N1 1 " "Info: 4: + IC(0.000 ns) + CELL(0.084 ns) = 0.803 ns; Loc. = LCFF_X63_Y20_N1; Fanout = 1; REG Node = 'inst'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { inst~feeder inst } "NODE_NAME" } } { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 104 264 328 184 "inst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.556 ns ( 69.24 % ) " "Info: Total cell delay = 0.556 ns ( 69.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.247 ns ( 30.76 % ) " "Info: Total interconnect delay = 0.247 ns ( 30.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.803 ns" { inst1 inst5 inst~feeder inst } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "0.803 ns" { inst1 inst5 inst~feeder inst } { 0.000ns 0.000ns 0.247ns 0.000ns } { 0.000ns 0.323ns 0.149ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.687 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.687 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 136 8 176 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 2 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 2; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 136 8 176 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.033 ns) + CELL(0.537 ns) 2.687 ns inst 3 REG LCFF_X63_Y20_N1 1 " "Info: 3: + IC(1.033 ns) + CELL(0.537 ns) = 2.687 ns; Loc. = LCFF_X63_Y20_N1; Fanout = 1; REG Node = 'inst'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.570 ns" { clk~clkctrl inst } "NODE_NAME" } } { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 104 264 328 184 "inst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.16 % ) " "Info: Total cell delay = 1.536 ns ( 57.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.151 ns ( 42.84 % ) " "Info: Total interconnect delay = 1.151 ns ( 42.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.687 ns" { clk clk~clkctrl inst } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.687 ns" { clk clk~combout clk~clkctrl inst } { 0.000ns 0.000ns 0.118ns 1.033ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.687 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.687 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 136 8 176 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 2 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 2; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 136 8 176 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.033 ns) + CELL(0.537 ns) 2.687 ns inst1 3 REG LCFF_X63_Y20_N31 1 " "Info: 3: + IC(1.033 ns) + CELL(0.537 ns) = 2.687 ns; Loc. = LCFF_X63_Y20_N31; Fanout = 1; REG Node = 'inst1'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.570 ns" { clk~clkctrl inst1 } "NODE_NAME" } } { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 216 264 328 296 "inst1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.16 % ) " "Info: Total cell delay = 1.536 ns ( 57.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.151 ns ( 42.84 % ) " "Info: Total interconnect delay = 1.151 ns ( 42.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.687 ns" { clk clk~clkctrl inst1 } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.687 ns" { clk clk~combout clk~clkctrl inst1 } { 0.000ns 0.000ns 0.118ns 1.033ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.687 ns" { clk clk~clkctrl inst } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.687 ns" { clk clk~combout clk~clkctrl inst } { 0.000ns 0.000ns 0.118ns 1.033ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.687 ns" { clk clk~clkctrl inst1 } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.687 ns" { clk clk~combout clk~clkctrl inst1 } { 0.000ns 0.000ns 0.118ns 1.033ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 216 264 328 296 "inst1" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 104 264 328 184 "inst" "" } } } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 216 264 328 296 "inst1" "" } } } } { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 104 264 328 184 "inst" "" } } } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.803 ns" { inst1 inst5 inst~feeder inst } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "0.803 ns" { inst1 inst5 inst~feeder inst } { 0.000ns 0.000ns 0.247ns 0.000ns } { 0.000ns 0.323ns 0.149ns 0.084ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.687 ns" { clk clk~clkctrl inst } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.687 ns" { clk clk~combout clk~clkctrl inst } { 0.000ns 0.000ns 0.118ns 1.033ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.687 ns" { clk clk~clkctrl inst1 } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.687 ns" { clk clk~combout clk~clkctrl inst1 } { 0.000ns 0.000ns 0.118ns 1.033ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { inst } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { inst } {  } {  } "" } } { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 104 264 328 184 "inst" "" } } } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk clk/3 inst2 7.644 ns register " "Info: tco from clock \"clk\" to destination pin \"clk/3\" through register \"inst2\" is 7.644 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 4.294 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 4.294 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 136 8 176 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 2 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 2; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 136 8 176 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.033 ns) + CELL(0.787 ns) 2.937 ns inst 3 REG LCFF_X63_Y20_N1 1 " "Info: 3: + IC(1.033 ns) + CELL(0.787 ns) = 2.937 ns; Loc. = LCFF_X63_Y20_N1; Fanout = 1; REG Node = 'inst'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.820 ns" { clk~clkctrl inst } "NODE_NAME" } } { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 104 264 328 184 "inst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.299 ns) + CELL(0.150 ns) 3.386 ns inst5 4 COMB LCCOMB_X63_Y20_N30 3 " "Info: 4: + IC(0.299 ns) + CELL(0.150 ns) = 3.386 ns; Loc. = LCCOMB_X63_Y20_N30; Fanout = 3; COMB Node = 'inst5'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.449 ns" { inst inst5 } "NODE_NAME" } } { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 160 352 416 208 "inst5" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.371 ns) + CELL(0.537 ns) 4.294 ns inst2 5 REG LCFF_X64_Y20_N31 2 " "Info: 5: + IC(0.371 ns) + CELL(0.537 ns) = 4.294 ns; Loc. = LCFF_X64_Y20_N31; Fanout = 2; REG Node = 'inst2'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.908 ns" { inst5 inst2 } "NODE_NAME" } } { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 144 464 528 224 "inst2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.473 ns ( 57.59 % ) " "Info: Total cell delay = 2.473 ns ( 57.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.821 ns ( 42.41 % ) " "Info: Total interconnect delay = 1.821 ns ( 42.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.294 ns" { clk clk~clkctrl inst inst5 inst2 } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "4.294 ns" { clk clk~combout clk~clkctrl inst inst5 inst2 } { 0.000ns 0.000ns 0.118ns 1.033ns 0.299ns 0.371ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.150ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 144 464 528 224 "inst2" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.100 ns + Longest register pin " "Info: + Longest register to pin delay is 3.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inst2 1 REG LCFF_X64_Y20_N31 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X64_Y20_N31; Fanout = 2; REG Node = 'inst2'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { inst2 } "NODE_NAME" } } { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 144 464 528 224 "inst2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.468 ns) + CELL(2.632 ns) 3.100 ns clk/3 2 PIN PIN_N23 0 " "Info: 2: + IC(0.468 ns) + CELL(2.632 ns) = 3.100 ns; Loc. = PIN_N23; Fanout = 0; PIN Node = 'clk/3'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.100 ns" { inst2 clk/3 } "NODE_NAME" } } { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 160 576 752 176 "clk/3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.632 ns ( 84.90 % ) " "Info: Total cell delay = 2.632 ns ( 84.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.468 ns ( 15.10 % ) " "Info: Total interconnect delay = 0.468 ns ( 15.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.100 ns" { inst2 clk/3 } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.100 ns" { inst2 clk/3 } { 0.000ns 0.468ns } { 0.000ns 2.632ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.294 ns" { clk clk~clkctrl inst inst5 inst2 } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "4.294 ns" { clk clk~combout clk~clkctrl inst inst5 inst2 } { 0.000ns 0.000ns 0.118ns 1.033ns 0.299ns 0.371ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.150ns 0.537ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.100 ns" { inst2 clk/3 } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.100 ns" { inst2 clk/3 } { 0.000ns 0.468ns } { 0.000ns 2.632ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "103 " "Info: Allocated 103 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 23 16:25:31 2008 " "Info: Processing ended: Tue Sep 23 16:25:31 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}