topmod.tan.qmsg

这是个128位的串行伪随机码发生器

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register divider3:inst\|inst1 divider3:inst\|inst 420.17 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 420.17 MHz between source register \"divider3:inst\|inst1\" and destination register \"divider3:inst\|inst\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.38 ns " "Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.803 ns + Longest register register " "Info: + Longest register to register delay is 0.803 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns divider3:inst\|inst1 1 REG LCFF_X63_Y23_N31 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X63_Y23_N31; Fanout = 1; REG Node = 'divider3:inst\|inst1'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { divider3:inst|inst1 } "NODE_NAME" } } { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 216 264 328 296 "inst1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.323 ns) 0.323 ns divider3:inst\|inst5 2 COMB LCCOMB_X63_Y23_N30 3 " "Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X63_Y23_N30; Fanout = 3; COMB Node = 'divider3:inst\|inst5'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.323 ns" { divider3:inst|inst1 divider3:inst|inst5 } "NODE_NAME" } } { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 160 352 416 208 "inst5" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.247 ns) + CELL(0.149 ns) 0.719 ns divider3:inst\|inst~feeder 3 COMB LCCOMB_X63_Y23_N0 1 " "Info: 3: + IC(0.247 ns) + CELL(0.149 ns) = 0.719 ns; Loc. = LCCOMB_X63_Y23_N0; Fanout = 1; COMB Node = 'divider3:inst\|inst~feeder'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.396 ns" { divider3:inst|inst5 divider3:inst|inst~feeder } "NODE_NAME" } } { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 104 264 328 184 "inst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.803 ns divider3:inst\|inst 4 REG LCFF_X63_Y23_N1 1 " "Info: 4: + IC(0.000 ns) + CELL(0.084 ns) = 0.803 ns; Loc. = LCFF_X63_Y23_N1; Fanout = 1; REG Node = 'divider3:inst\|inst'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { divider3:inst|inst~feeder divider3:inst|inst } "NODE_NAME" } } { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 104 264 328 184 "inst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.556 ns ( 69.24 % ) " "Info: Total cell delay = 0.556 ns ( 69.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.247 ns ( 30.76 % ) " "Info: Total interconnect delay = 0.247 ns ( 30.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.803 ns" { divider3:inst|inst1 divider3:inst|inst5 divider3:inst|inst~feeder divider3:inst|inst } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "0.803 ns" { divider3:inst|inst1 divider3:inst|inst5 divider3:inst|inst~feeder divider3:inst|inst } { 0.000ns 0.000ns 0.247ns 0.000ns } { 0.000ns 0.323ns 0.149ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.678 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.678 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "topmod.bdf" "" { Schematic "E:/lcp/pn127/topmod.bdf" { { 48 0 168 64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 2 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 2; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "topmod.bdf" "" { Schematic "E:/lcp/pn127/topmod.bdf" { { 48 0 168 64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.024 ns) + CELL(0.537 ns) 2.678 ns divider3:inst\|inst 3 REG LCFF_X63_Y23_N1 1 " "Info: 3: + IC(1.024 ns) + CELL(0.537 ns) = 2.678 ns; Loc. = LCFF_X63_Y23_N1; Fanout = 1; REG Node = 'divider3:inst\|inst'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.561 ns" { clk~clkctrl divider3:inst|inst } "NODE_NAME" } } { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 104 264 328 184 "inst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.36 % ) " "Info: Total cell delay = 1.536 ns ( 57.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.142 ns ( 42.64 % ) " "Info: Total interconnect delay = 1.142 ns ( 42.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.678 ns" { clk clk~clkctrl divider3:inst|inst } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.678 ns" { clk clk~combout clk~clkctrl divider3:inst|inst } { 0.000ns 0.000ns 0.118ns 1.024ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.678 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.678 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "topmod.bdf" "" { Schematic "E:/lcp/pn127/topmod.bdf" { { 48 0 168 64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 2 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 2; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "topmod.bdf" "" { Schematic "E:/lcp/pn127/topmod.bdf" { { 48 0 168 64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.024 ns) + CELL(0.537 ns) 2.678 ns divider3:inst\|inst1 3 REG LCFF_X63_Y23_N31 1 " "Info: 3: + IC(1.024 ns) + CELL(0.537 ns) = 2.678 ns; Loc. = LCFF_X63_Y23_N31; Fanout = 1; REG Node = 'divider3:inst\|inst1'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.561 ns" { clk~clkctrl divider3:inst|inst1 } "NODE_NAME" } } { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 216 264 328 296 "inst1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.36 % ) " "Info: Total cell delay = 1.536 ns ( 57.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.142 ns ( 42.64 % ) " "Info: Total interconnect delay = 1.142 ns ( 42.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.678 ns" { clk clk~clkctrl divider3:inst|inst1 } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.678 ns" { clk clk~combout clk~clkctrl divider3:inst|inst1 } { 0.000ns 0.000ns 0.118ns 1.024ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.678 ns" { clk clk~clkctrl divider3:inst|inst } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.678 ns" { clk clk~combout clk~clkctrl divider3:inst|inst } { 0.000ns 0.000ns 0.118ns 1.024ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.678 ns" { clk clk~clkctrl divider3:inst|inst1 } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.678 ns" { clk clk~combout clk~clkctrl divider3:inst|inst1 } { 0.000ns 0.000ns 0.118ns 1.024ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 216 264 328 296 "inst1" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 104 264 328 184 "inst" "" } } } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 216 264 328 296 "inst1" "" } } } } { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 104 264 328 184 "inst" "" } } } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.803 ns" { divider3:inst|inst1 divider3:inst|inst5 divider3:inst|inst~feeder divider3:inst|inst } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "0.803 ns" { divider3:inst|inst1 divider3:inst|inst5 divider3:inst|inst~feeder divider3:inst|inst } { 0.000ns 0.000ns 0.247ns 0.000ns } { 0.000ns 0.323ns 0.149ns 0.084ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.678 ns" { clk clk~clkctrl divider3:inst|inst } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.678 ns" { clk clk~combout clk~clkctrl divider3:inst|inst } { 0.000ns 0.000ns 0.118ns 1.024ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.678 ns" { clk clk~clkctrl divider3:inst|inst1 } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.678 ns" { clk clk~combout clk~clkctrl divider3:inst|inst1 } { 0.000ns 0.000ns 0.118ns 1.024ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { divider3:inst|inst } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { divider3:inst|inst } {  } {  } "" } } { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 104 264 328 184 "inst" "" } } } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk pn127 pn127:inst1\|inst6 10.669 ns register " "Info: tco from clock \"clk\" to destination pin \"pn127\" through register \"pn127:inst1\|inst6\" is 10.669 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.011 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.011 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "topmod.bdf" "" { Schematic "E:/lcp/pn127/topmod.bdf" { { 48 0 168 64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 2 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 2; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "topmod.bdf" "" { Schematic "E:/lcp/pn127/topmod.bdf" { { 48 0 168 64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.024 ns) + CELL(0.787 ns) 2.928 ns divider3:inst\|inst 3 REG LCFF_X63_Y23_N1 1 " "Info: 3: + IC(1.024 ns) + CELL(0.787 ns) = 2.928 ns; Loc. = LCFF_X63_Y23_N1; Fanout = 1; REG Node = 'divider3:inst\|inst'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.811 ns" { clk~clkctrl divider3:inst|inst } "NODE_NAME" } } { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 104 264 328 184 "inst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.299 ns) + CELL(0.150 ns) 3.377 ns divider3:inst\|inst5 4 COMB LCCOMB_X63_Y23_N30 3 " "Info: 4: + IC(0.299 ns) + CELL(0.150 ns) = 3.377 ns; Loc. = LCCOMB_X63_Y23_N30; Fanout = 3; COMB Node = 'divider3:inst\|inst5'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.449 ns" { divider3:inst|inst divider3:inst|inst5 } "NODE_NAME" } } { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 160 352 416 208 "inst5" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.371 ns) + CELL(0.787 ns) 4.535 ns divider3:inst\|inst2 5 REG LCFF_X64_Y23_N31 2 " "Info: 5: + IC(0.371 ns) + CELL(0.787 ns) = 4.535 ns; Loc. = LCFF_X64_Y23_N31; Fanout = 2; REG Node = 'divider3:inst\|inst2'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.158 ns" { divider3:inst|inst5 divider3:inst|inst2 } "NODE_NAME" } } { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 144 464 528 224 "inst2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.892 ns) + CELL(0.000 ns) 5.427 ns divider3:inst\|inst2~clkctrl 6 COMB CLKCTRL_G5 7 " "Info: 6: + IC(0.892 ns) + CELL(0.000 ns) = 5.427 ns; Loc. = CLKCTRL_G5; Fanout = 7; COMB Node = 'divider3:inst\|inst2~clkctrl'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.892 ns" { divider3:inst|inst2 divider3:inst|inst2~clkctrl } "NODE_NAME" } } { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 144 464 528 224 "inst2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.047 ns) + CELL(0.537 ns) 7.011 ns pn127:inst1\|inst6 7 REG LCFF_X25_Y35_N19 3 " "Info: 7: + IC(1.047 ns) + CELL(0.537 ns) = 7.011 ns; Loc. = LCFF_X25_Y35_N19; Fanout = 3; REG Node = 'pn127:inst1\|inst6'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.584 ns" { divider3:inst|inst2~clkctrl pn127:inst1|inst6 } "NODE_NAME" } } { "pn127.bdf" "" { Schematic "E:/lcp/pn127/pn127.bdf" { { 152 696 760 232 "inst6" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.260 ns ( 46.50 % ) " "Info: Total cell delay = 3.260 ns ( 46.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.751 ns ( 53.50 % ) " "Info: Total interconnect delay = 3.751 ns ( 53.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.011 ns" { clk clk~clkctrl divider3:inst|inst divider3:inst|inst5 divider3:inst|inst2 divider3:inst|inst2~clkctrl pn127:inst1|inst6 } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.011 ns" { clk clk~combout clk~clkctrl divider3:inst|inst divider3:inst|inst5 divider3:inst|inst2 divider3:inst|inst2~clkctrl pn127:inst1|inst6 } { 0.000ns 0.000ns 0.118ns 1.024ns 0.299ns 0.371ns 0.892ns 1.047ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.150ns 0.787ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "pn127.bdf" "" { Schematic "E:/lcp/pn127/pn127.bdf" { { 152 696 760 232 "inst6" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.408 ns + Longest register pin " "Info: + Longest register to pin delay is 3.408 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pn127:inst1\|inst6 1 REG LCFF_X25_Y35_N19 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X25_Y35_N19; Fanout = 3; REG Node = 'pn127:inst1\|inst6'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { pn127:inst1|inst6 } "NODE_NAME" } } { "pn127.bdf" "" { Schematic "E:/lcp/pn127/pn127.bdf" { { 152 696 760 232 "inst6" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.630 ns) + CELL(2.778 ns) 3.408 ns pn127 2 PIN PIN_J14 0 " "Info: 2: + IC(0.630 ns) + CELL(2.778 ns) = 3.408 ns; Loc. = PIN_J14; Fanout = 0; PIN Node = 'pn127'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.408 ns" { pn127:inst1|inst6 pn127 } "NODE_NAME" } } { "topmod.bdf" "" { Schematic "E:/lcp/pn127/topmod.bdf" { { 48 456 632 64 "pn127" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.778 ns ( 81.51 % ) " "Info: Total cell delay = 2.778 ns ( 81.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.630 ns ( 18.49 % ) " "Info: Total interconnect delay = 0.630 ns ( 18.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.408 ns" { pn127:inst1|inst6 pn127 } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.408 ns" { pn127:inst1|inst6 pn127 } { 0.000ns 0.630ns } { 0.000ns 2.778ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.011 ns" { clk clk~clkctrl divider3:inst|inst divider3:inst|inst5 divider3:inst|inst2 divider3:inst|inst2~clkctrl pn127:inst1|inst6 } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.011 ns" { clk clk~combout clk~clkctrl divider3:inst|inst divider3:inst|inst5 divider3:inst|inst2 divider3:inst|inst2~clkctrl pn127:inst1|inst6 } { 0.000ns 0.000ns 0.118ns 1.024ns 0.299ns 0.371ns 0.892ns 1.047ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.150ns 0.787ns 0.000ns 0.537ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.408 ns" { pn127:inst1|inst6 pn127 } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.408 ns" { pn127:inst1|inst6 pn127 } { 0.000ns 0.630ns } { 0.000ns 2.778ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "103 " "Info: Allocated 103 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 23 16:30:59 2008 " "Info: Processing ended: Tue Sep 23 16:30:59 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}