topmod.tan.qmsg

这是个128位的串行伪随机码发生器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.1 Build 201 11/27/2006 SJ Full Version " "Info: Version 6.1 Build 201 11/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 23 16:30:59 2008 " "Info: Processing started: Tue Sep 23 16:30:59 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off topmod -c topmod --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off topmod -c topmod --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "topmod.bdf" "" { Schematic "E:/lcp/pn127/topmod.bdf" { { 48 0 168 64 "clk" "" } } } } { "c:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "4 " "Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "divider3:inst\|inst " "Info: Detected ripple clock \"divider3:inst\|inst\" as buffer" {  } { { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 104 264 328 184 "inst" "" } } } } { "c:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "divider3:inst\|inst" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "divider3:inst\|inst1 " "Info: Detected ripple clock \"divider3:inst\|inst1\" as buffer" {  } { { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 216 264 328 296 "inst1" "" } } } } { "c:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "divider3:inst\|inst1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "divider3:inst\|inst5 " "Info: Detected gated clock \"divider3:inst\|inst5\" as buffer" {  } { { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 160 352 416 208 "inst5" "" } } } } { "c:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "divider3:inst\|inst5" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "divider3:inst\|inst2 " "Info: Detected ripple clock \"divider3:inst\|inst2\" as buffer" {  } { { "divider3.bdf" "" { Schematic "E:/lcp/pn127/divider3.bdf" { { 144 464 528 224 "inst2" "" } } } } { "c:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "divider3:inst\|inst2" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}