📄 divider3.tan.rpt
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Classic Timing Analyzer report for divider3
Tue Sep 23 16:25:31 2008
Quartus II Version 6.1 Build 201 11/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tco
7. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+-------+-------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+-------+-------+------------+----------+--------------+
; Worst-case tco ; N/A ; None ; 7.644 ns ; inst2 ; clk/3 ; clk ; -- ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; inst1 ; inst ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+-------+-------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C35F672C6 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+-------+-------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-------+-------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; inst1 ; inst ; clk ; clk ; None ; None ; 0.803 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; inst ; inst1 ; clk ; clk ; None ; None ; 0.533 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; inst ; inst ; clk ; clk ; None ; None ; 0.929 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; inst2 ; inst2 ; clk ; clk ; None ; None ; 0.407 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; inst1 ; inst1 ; clk ; clk ; None ; None ; 0.407 ns ;
+-------+------------------------------------------------+-------+-------+------------+----------+-----------------------------+---------------------------+-------------------------+
+----------------------------------------------------------------+
; tco ;
+-------+--------------+------------+-------+-------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+-------+-------+------------+
; N/A ; None ; 7.644 ns ; inst2 ; clk/3 ; clk ;
+-------+--------------+------------+-------+-------+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
Info: Processing started: Tue Sep 23 16:25:31 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off divider3 -c divider3 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
Info: Detected ripple clock "inst" as buffer
Info: Detected ripple clock "inst1" as buffer
Info: Detected gated clock "inst5" as buffer
Info: Clock "clk" Internal fmax is restricted to 420.17 MHz between source register "inst1" and destination register "inst"
Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 0.803 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X63_Y20_N31; Fanout = 1; REG Node = 'inst1'
Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X63_Y20_N30; Fanout = 3; COMB Node = 'inst5'
Info: 3: + IC(0.247 ns) + CELL(0.149 ns) = 0.719 ns; Loc. = LCCOMB_X63_Y20_N0; Fanout = 1; COMB Node = 'inst~feeder'
Info: 4: + IC(0.000 ns) + CELL(0.084 ns) = 0.803 ns; Loc. = LCFF_X63_Y20_N1; Fanout = 1; REG Node = 'inst'
Info: Total cell delay = 0.556 ns ( 69.24 % )
Info: Total interconnect delay = 0.247 ns ( 30.76 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clk" to destination register is 2.687 ns
Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 2; COMB Node = 'clk~clkctrl'
Info: 3: + IC(1.033 ns) + CELL(0.537 ns) = 2.687 ns; Loc. = LCFF_X63_Y20_N1; Fanout = 1; REG Node = 'inst'
Info: Total cell delay = 1.536 ns ( 57.16 % )
Info: Total interconnect delay = 1.151 ns ( 42.84 % )
Info: - Longest clock path from clock "clk" to source register is 2.687 ns
Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 2; COMB Node = 'clk~clkctrl'
Info: 3: + IC(1.033 ns) + CELL(0.537 ns) = 2.687 ns; Loc. = LCFF_X63_Y20_N31; Fanout = 1; REG Node = 'inst1'
Info: Total cell delay = 1.536 ns ( 57.16 % )
Info: Total interconnect delay = 1.151 ns ( 42.84 % )
Info: + Micro clock to output delay of source is 0.250 ns
Info: + Micro setup delay of destination is -0.036 ns
Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two
Info: tco from clock "clk" to destination pin "clk/3" through register "inst2" is 7.644 ns
Info: + Longest clock path from clock "clk" to source register is 4.294 ns
Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 2; COMB Node = 'clk~clkctrl'
Info: 3: + IC(1.033 ns) + CELL(0.787 ns) = 2.937 ns; Loc. = LCFF_X63_Y20_N1; Fanout = 1; REG Node = 'inst'
Info: 4: + IC(0.299 ns) + CELL(0.150 ns) = 3.386 ns; Loc. = LCCOMB_X63_Y20_N30; Fanout = 3; COMB Node = 'inst5'
Info: 5: + IC(0.371 ns) + CELL(0.537 ns) = 4.294 ns; Loc. = LCFF_X64_Y20_N31; Fanout = 2; REG Node = 'inst2'
Info: Total cell delay = 2.473 ns ( 57.59 % )
Info: Total interconnect delay = 1.821 ns ( 42.41 % )
Info: + Micro clock to output delay of source is 0.250 ns
Info: + Longest register to pin delay is 3.100 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X64_Y20_N31; Fanout = 2; REG Node = 'inst2'
Info: 2: + IC(0.468 ns) + CELL(2.632 ns) = 3.100 ns; Loc. = PIN_N23; Fanout = 0; PIN Node = 'clk/3'
Info: Total cell delay = 2.632 ns ( 84.90 % )
Info: Total interconnect delay = 0.468 ns ( 15.10 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
Info: Allocated 103 megabytes of memory during processing
Info: Processing ended: Tue Sep 23 16:25:31 2008
Info: Elapsed time: 00:00:00
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