divider3.merge.rpt

这是个128位的串行伪随机码发生器

Partition Merge report for divider3
Tue Sep 23 16:24:55 2008
Quartus II Version 6.1 Build 201 11/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Partition Merge Summary
  3. Partition Merge Netlist Types Used
  4. Partition Merge Partition Statistics
  5. Partition Merge Resource Usage Summary
  6. Partition Merge Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; Partition Merge Summary                                                       ;
+------------------------------------+------------------------------------------+
; Partition Merge Status             ; Successful - Tue Sep 23 16:24:55 2008    ;
; Quartus II Version                 ; 6.1 Build 201 11/27/2006 SJ Full Version ;
; Revision Name                      ; divider3                                 ;
; Top-level Entity Name              ; divider3                                 ;
; Family                             ; Cyclone II                               ;
; Total logic elements               ; 3                                        ;
;     Total combinational functions  ; 2                                        ;
;     Dedicated logic registers      ; 3                                        ;
; Total registers                    ; 3                                        ;
; Total pins                         ; 2                                        ;
; Total virtual pins                 ; 0                                        ;
; Total memory bits                  ; 0                                        ;
; Embedded Multiplier 9-bit elements ; 0                                        ;
; Total PLLs                         ; 0                                        ;
+------------------------------------+------------------------------------------+


+---------------------------------------------------------------------------------------+
; Partition Merge Netlist Types Used                                                    ;
+----------------+------------------------+------------------------+--------------------+
; Partition Name ; Netlist Type Used      ; Netlist Type Requested ; Partition Contents ;
+----------------+------------------------+------------------------+--------------------+
; Top            ; Post-Synthesis Netlist ; Post-Synthesis Netlist ;                    ;
+----------------+------------------------+------------------------+--------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Partition Merge Partition Statistics                                                                                                                                                                                                                                                                            ;
+----------------+-------------------------------+-------------+-----------------+-----------------+-------------+--------------+------------------------+-------------------------+-------------------------+--------------------------+---------------------------+------------------------+--------------------+
; Partition Name ; Total combinational functions ; normal mode ; arithmetic mode ; Total registers ; Input Ports ; Output Ports ; Registered Input Ports ; Registered Output Ports ; Unconnected Input Ports ; Unconnected Output Ports ; Driven Ground Input Ports ; Driven VCC Input Ports ; Partition Contents ;
+----------------+-------------------------------+-------------+-----------------+-----------------+-------------+--------------+------------------------+-------------------------+-------------------------+--------------------------+---------------------------+------------------------+--------------------+
; Top            ; 2                             ; 2           ; 0               ; 3               ; 1           ; 1            ; 1                      ; 1                       ; N/A                     ; N/A                      ; N/A                       ; N/A                    ;                    ;
+----------------+-------------------------------+-------------+-----------------+-----------------+-------------+--------------+------------------------+-------------------------+-------------------------+--------------------------+---------------------------+------------------------+--------------------+


+-----------------------------------------------------+
; Partition Merge Resource Usage Summary              ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 3     ;
;                                             ;       ;
; Total combinational functions               ; 2     ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 0     ;
;     -- 3 input functions                    ; 0     ;
;     -- <=2 input functions                  ; 2     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 2     ;
;     -- arithmetic mode                      ; 0     ;
;                                             ;       ;
; Total registers                             ; 3     ;
;     -- Dedicated logic registers            ; 3     ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 2     ;
; Maximum fan-out node                        ; inst5 ;
; Maximum fan-out                             ; 3     ;
; Total fan-out                               ; 10    ;
; Average fan-out                             ; 1.43  ;
+---------------------------------------------+-------+


+--------------------------+
; Partition Merge Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Partition Merge
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Tue Sep 23 16:24:55 2008
Info: Command: quartus_cdb --read_settings_files=off --write_settings_files=off divider3 -c divider3 --merge=on
Info: Using synthesis netlist for partition "Top"
Info: Netlist merging resolved 1 partition(s) out of the 1 partition(s) found
Info: Quartus II Partition Merge was successful. 0 errors, 0 warnings
    Info: Allocated 97 megabytes of memory during processing
    Info: Processing ended: Tue Sep 23 16:24:55 2008
    Info: Elapsed time: 00:00:00