divider3.fit.smsg

这是个128位的串行伪随机码发生器

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Tue Sep 23 16:24:56 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off divider3 -c divider3
Info: Selected device EP2C35F672C6 for design "divider3"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 7 of 7 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP2C50F672C6 is compatible
    Info: Device EP2C70F672C6 is compatible
Info: Fitter converted 3 user pins into dedicated programming pins
    Info: Pin ~ASDO~ is reserved at location E3
    Info: Pin ~nCSO~ is reserved at location D3
    Info: Pin ~LVDS150p/nCEO~ is reserved at location AE24
Warning: No exact pin location assignment(s) for 2 pins of 2 total pins
    Info: Pin clk/3 not assigned to an exact location on the device
    Info: Pin clk not assigned to an exact location on the device
Info: Automatically promoted node clk (placed in PIN P2 (CLK2, LVDSCLK1p, Input))
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:00
    Extra Info: No registers were packed into other blocks
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 1 (unused VREF, 3.30 VCCIO, 0 input, 1 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  63 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  57 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  56 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  58 pins available
        Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  65 pins available
        Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  58 pins available
        Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  58 pins available
        Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  56 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 0.989 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X63_Y20; Fanout = 1; REG Node = 'inst1'
    Info: 2: + IC(0.110 ns) + CELL(0.398 ns) = 0.508 ns; Loc. = LAB_X63_Y20; Fanout = 3; COMB Node = 'inst5'
    Info: 3: + IC(0.397 ns) + CELL(0.084 ns) = 0.989 ns; Loc. = LAB_X63_Y20; Fanout = 1; REG Node = 'inst'
    Info: Total cell delay = 0.482 ns ( 48.74 % )
    Info: Total interconnect delay = 0.507 ns ( 51.26 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%
    Info: The peak interconnect region extends from location X0_Y24 to location X10_Y36
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Started post-fitting delay annotation
Warning: Found 1 output pins without output pin load capacitance assignment
    Info: Pin "clk/3" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 3 warnings
    Info: Allocated 221 megabytes of memory during processing
    Info: Processing ended: Tue Sep 23 16:25:12 2008
    Info: Elapsed time: 00:00:16