topmod.map.rpt

这是个128位的串行伪随机码发生器

; HDL message level                                                  ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                    ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report           ; 100                ; 100                ;
; Use smart compilation                                              ; Off                ; Off                ;
+--------------------------------------------------------------------+--------------------+--------------------+


+-----------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                        ;
+----------------------------------+-----------------+-----------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------+------------------------------+
; topmod.bdf                       ; yes             ; Other     ; E:/lcp/pn127/topmod.bdf      ;
; pn127.bdf                        ; yes             ; Other     ; E:/lcp/pn127/pn127.bdf       ;
; divider3.bdf                     ; yes             ; Other     ; E:/lcp/pn127/divider3.bdf    ;
+----------------------------------+-----------------+-----------+------------------------------+


+-------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                       ;
+---------------------------------------------+---------------------+
; Resource                                    ; Usage               ;
+---------------------------------------------+---------------------+
; Estimated Total logic elements              ; 10                  ;
;                                             ;                     ;
; Total combinational functions               ; 7                   ;
; Logic element usage by number of LUT inputs ;                     ;
;     -- 4 input functions                    ; 2                   ;
;     -- 3 input functions                    ; 0                   ;
;     -- <=2 input functions                  ; 5                   ;
;                                             ;                     ;
; Logic elements by mode                      ;                     ;
;     -- normal mode                          ; 7                   ;
;     -- arithmetic mode                      ; 0                   ;
;                                             ;                     ;
; Total registers                             ; 10                  ;
;     -- Dedicated logic registers            ; 10                  ;
;     -- I/O registers                        ; 0                   ;
;                                             ;                     ;
; I/O pins                                    ; 0                   ;
; Maximum fan-out node                        ; divider3:inst|inst2 ;
; Maximum fan-out                             ; 8                   ;
; Total fan-out                               ; 37                  ;
; Average fan-out                             ; 1.95                ;
+---------------------------------------------+---------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                            ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name   ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------+
; |topmod                    ; 7 (0)             ; 10 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |topmod               ;
;    |divider3:inst|         ; 2 (2)             ; 3 (3)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |topmod|divider3:inst ;
;    |pn127:inst1|           ; 5 (5)             ; 7 (7)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |topmod|pn127:inst1   ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 10    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 1     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; pn127:inst1|inst3                      ; 2       ;
; Total number of inverted registers = 1 ;         ;
+----------------------------------------+---------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Tue Sep 23 16:30:23 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off topmod -c topmod
Warning: Using design file topmod.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: topmod
Info: Elaborating entity "topmod" for the top level hierarchy
Warning: Using design file pn127.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: pn127
Info: Elaborating entity "pn127" for hierarchy "pn127:inst1"
Warning: Using design file divider3.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: divider3
Info: Elaborating entity "divider3" for hierarchy "divider3:inst"
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info: Implemented 15 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 1 output pins
    Info: Implemented 13 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
    Info: Allocated 119 megabytes of memory during processing
    Info: Processing ended: Tue Sep 23 16:30:24 2008
    Info: Elapsed time: 00:00:01