📄 prev_cmp_jianzhong.tan.qmsg
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{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "f\[0\] " "Warning: Node \"f\[0\]\"" { } { { "jianzhong.vhd" "" { Text "E:/EDA/林璐雅/时钟按键1/jianzhong.vhd" 11 -1 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0} } { { "jianzhong.vhd" "" { Text "E:/EDA/林璐雅/时钟按键1/jianzhong.vhd" 11 -1 0 } } } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0}
{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "f\[1\] " "Warning: Node \"f\[1\]\"" { } { { "jianzhong.vhd" "" { Text "E:/EDA/林璐雅/时钟按键1/jianzhong.vhd" 11 -1 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0} } { { "jianzhong.vhd" "" { Text "E:/EDA/林璐雅/时钟按键1/jianzhong.vhd" 11 -1 0 } } } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0}
{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "f\[2\] " "Warning: Node \"f\[2\]\"" { } { { "jianzhong.vhd" "" { Text "E:/EDA/林璐雅/时钟按键1/jianzhong.vhd" 11 -1 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0} } { { "jianzhong.vhd" "" { Text "E:/EDA/林璐雅/时钟按键1/jianzhong.vhd" 11 -1 0 } } } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "jianzhong.vhd" "" { Text "E:/EDA/林璐雅/时钟按键1/jianzhong.vhd" 2 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register lpm_counter:\\x2:i\[0\]_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[3\] register lpm_counter:c_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\] 64.1 MHz 15.6 ns Internal " "Info: Clock \"clk\" has Internal fmax of 64.1 MHz between source register \"lpm_counter:\\x2:i\[0\]_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[3\]\" and destination register \"lpm_counter:c_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\]\" (period= 15.6 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.200 ns + Longest register register " "Info: + Longest register to register delay is 14.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:\\x2:i\[0\]_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[3\] 1 REG LC7_H5 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_H5; Fanout = 3; REG Node = 'lpm_counter:\\x2:i\[0\]_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[3\]'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_counter:\x2:i[0]_rtl_2|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/program files/altera/72/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(1.500 ns) 2.700 ns LessThan0~95 2 COMB LC8_H7 1 " "Info: 2: + IC(1.200 ns) + CELL(1.500 ns) = 2.700 ns; Loc. = LC8_H7; Fanout = 1; COMB Node = 'LessThan0~95'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.700 ns" { lpm_counter:\x2:i[0]_rtl_2|alt_counter_f10ke:wysi_counter|q[3] LessThan0~95 } "NODE_NAME" } } { "jianzhong.vhd" "" { Text "E:/EDA/林璐雅/时钟按键1/jianzhong.vhd" 35 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.400 ns) 4.300 ns LessThan0~96 3 COMB LC6_H7 11 " "Info: 3: + IC(0.200 ns) + CELL(1.400 ns) = 4.300 ns; Loc. = LC6_H7; Fanout = 11; COMB Node = 'LessThan0~96'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { LessThan0~95 LessThan0~96 } "NODE_NAME" } } { "jianzhong.vhd" "" { Text "E:/EDA/林璐雅/时钟按键1/jianzhong.vhd" 35 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(1.600 ns) 7.100 ns lpm_counter:a_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[3\]~115 4 COMB LC2_H8 5 " "Info: 4: + IC(1.200 ns) + CELL(1.600 ns) = 7.100 ns; Loc. = LC2_H8; Fanout = 5; COMB Node = 'lpm_counter:a_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[3\]~115'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.800 ns" { LessThan0~96 lpm_counter:a_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~115 } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/program files/altera/72/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 329 15 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.500 ns) 8.800 ns d\[2\]~155 5 COMB LC1_H8 10 " "Info: 5: + IC(0.200 ns) + CELL(1.500 ns) = 8.800 ns; Loc. = LC1_H8; Fanout = 10; COMB Node = 'd\[2\]~155'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { lpm_counter:a_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~115 d[2]~155 } "NODE_NAME" } } { "jianzhong.vhd" "" { Text "E:/EDA/林璐雅/时钟按键1/jianzhong.vhd" 33 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(1.400 ns) 11.400 ns lpm_counter:c_rtl_1\|alt_counter_f10ke:wysi_counter\|counter_cell\[3\]~126 6 COMB LC1_H10 4 " "Info: 6: + IC(1.200 ns) + CELL(1.400 ns) = 11.400 ns; Loc. = LC1_H10; Fanout = 4; COMB Node = 'lpm_counter:c_rtl_1\|alt_counter_f10ke:wysi_counter\|counter_cell\[3\]~126'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.600 ns" { d[2]~155 lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3]~126 } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/program files/altera/72/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 329 15 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.400 ns) 13.000 ns lpm_counter:c_rtl_1\|alt_counter_f10ke:wysi_counter\|counter_cell\[3\]~126_wirecell 7 COMB LC3_H10 4 " "Info: 7: + IC(0.200 ns) + CELL(1.400 ns) = 13.000 ns; Loc. = LC3_H10; Fanout = 4; COMB Node = 'lpm_counter:c_rtl_1\|alt_counter_f10ke:wysi_counter\|counter_cell\[3\]~126_wirecell'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3]~126 lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3]~126_wirecell } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/program files/altera/72/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 329 15 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.000 ns) 14.200 ns lpm_counter:c_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\] 8 REG LC7_H10 16 " "Info: 8: + IC(0.200 ns) + CELL(1.000 ns) = 14.200 ns; Loc. = LC7_H10; Fanout = 16; REG Node = 'lpm_counter:c_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\]'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.200 ns" { lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3]~126_wirecell lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/program files/altera/72/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.800 ns ( 69.01 % ) " "Info: Total cell delay = 9.800 ns ( 69.01 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.400 ns ( 30.99 % ) " "Info: Total interconnect delay = 4.400 ns ( 30.99 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "14.200 ns" { lpm_counter:\x2:i[0]_rtl_2|alt_counter_f10ke:wysi_counter|q[3] LessThan0~95 LessThan0~96 lpm_counter:a_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~115 d[2]~155 lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3]~126 lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3]~126_wirecell lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "14.200 ns" { lpm_counter:\x2:i[0]_rtl_2|alt_counter_f10ke:wysi_counter|q[3] {} LessThan0~95 {} LessThan0~96 {} lpm_counter:a_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~115 {} d[2]~155 {} lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3]~126 {} lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3]~126_wirecell {} lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|q[3] {} } { 0.000ns 1.200ns 0.200ns 1.200ns 0.200ns 1.200ns 0.200ns 0.200ns } { 0.000ns 1.500ns 1.400ns 1.600ns 1.500ns 1.400ns 1.400ns 1.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.500 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns clk 1 CLK PIN_79 35 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_79; Fanout = 35; CLK Node = 'clk'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jianzhong.vhd" "" { Text "E:/EDA/林璐雅/时钟按键1/jianzhong.vhd" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 3.500 ns lpm_counter:c_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\] 2 REG LC7_H10 16 " "Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC7_H10; Fanout = 16; REG Node = 'lpm_counter:c_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\]'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.300 ns" { clk lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/program files/altera/72/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 62.86 % ) " "Info: Total cell delay = 2.200 ns ( 62.86 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 37.14 % ) " "Info: Total interconnect delay = 1.300 ns ( 37.14 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { clk lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { clk {} clk~out {} lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|q[3] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.500 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns clk 1 CLK PIN_79 35 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_79; Fanout = 35; CLK Node = 'clk'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jianzhong.vhd" "" { Text "E:/EDA/林璐雅/时钟按键1/jianzhong.vhd" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 3.500 ns lpm_counter:\\x2:i\[0\]_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[3\] 2 REG LC7_H5 3 " "Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC7_H5; Fanout = 3; REG Node = 'lpm_counter:\\x2:i\[0\]_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[3\]'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.300 ns" { clk lpm_counter:\x2:i[0]_rtl_2|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/program files/altera/72/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 62.86 % ) " "Info: Total cell delay = 2.200 ns ( 62.86 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 37.14 % ) " "Info: Total interconnect delay = 1.300 ns ( 37.14 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { clk lpm_counter:\x2:i[0]_rtl_2|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { clk {} clk~out {} lpm_counter:\x2:i[0]_rtl_2|alt_counter_f10ke:wysi_counter|q[3] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { clk lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { clk {} clk~out {} lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|q[3] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { clk lpm_counter:\x2:i[0]_rtl_2|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { clk {} clk~out {} lpm_counter:\x2:i[0]_rtl_2|alt_counter_f10ke:wysi_counter|q[3] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.700 ns + " "Info: + Micro clock to output delay of source is 0.700 ns" { } { { "alt_counter_f10ke.tdf" "" { Text "d:/program files/altera/72/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" { } { { "alt_counter_f10ke.tdf" "" { Text "d:/program files/altera/72/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "14.200 ns" { lpm_counter:\x2:i[0]_rtl_2|alt_counter_f10ke:wysi_counter|q[3] LessThan0~95 LessThan0~96 lpm_counter:a_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~115 d[2]~155 lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3]~126 lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3]~126_wirecell lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "14.200 ns" { lpm_counter:\x2:i[0]_rtl_2|alt_counter_f10ke:wysi_counter|q[3] {} LessThan0~95 {} LessThan0~96 {} lpm_counter:a_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~115 {} d[2]~155 {} lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3]~126 {} lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3]~126_wirecell {} lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|q[3] {} } { 0.000ns 1.200ns 0.200ns 1.200ns 0.200ns 1.200ns 0.200ns 0.200ns } { 0.000ns 1.500ns 1.400ns 1.600ns 1.500ns 1.400ns 1.400ns 1.000ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { clk lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { clk {} clk~out {} lpm_counter:c_rtl_1|alt_counter_f10ke:wysi_counter|q[3] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { clk lpm_counter:\x2:i[0]_rtl_2|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { clk {} clk~out {} lpm_counter:\x2:i[0]_rtl_2|alt_counter_f10ke:wysi_counter|q[3] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "\\x3:t\[1\] s5 clk 24.900 ns register " "Info: tsu for register \"\\x3:t\[1\]\" (data pin = \"s5\", clock pin = \"clk\") is 24.900 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "27.700 ns + Longest pin register " "Info: + Longest pin to register delay is 27.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns s5 1 PIN PIN_46 4 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_46; Fanout = 4; PIN Node = 's5'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { s5 } "NODE_NAME" } } { "jianzhong.vhd" "" { Text "E:/EDA/林璐雅/时钟按键1/jianzhong.vhd" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.700 ns) + CELL(1.500 ns) 9.200 ns f\[0\]~297 2 COMB LC2_I24 1 " "Info: 2: + IC(4.700 ns) + CELL(1.500 ns) = 9.200 ns; Loc. = LC2_I24; Fanout = 1; COMB Node = 'f\[0\]~297'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.200 ns" { s5 f[0]~297 } "NODE_NAME" } } { "jianzhong.vhd" "" { Text "E:/EDA/林璐雅/时钟按键1/jianzhong.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(1.500 ns) 12.200 ns comb~270 3 COMB LC4_I34 3 " "Info: 3: + IC(1.500 ns) + CELL(1.500 ns) = 12.200 ns; Loc. = LC4_I34; Fanout = 3; COMB Node = 'comb~270'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { f[0]~297 comb~270 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(1.500 ns) 15.000 ns comb~2 4 COMB LC1_I30 2 " "Info: 4: + IC(1.300 ns) + CELL(1.500 ns) = 15.000 ns; Loc. = LC1_I30; Fanout = 2; COMB Node = 'comb~2'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.800 ns" { comb~270 comb~2 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.700 ns) 16.700 ns f\[0\] 5 COMB LOOP LC2_I30 15 " "Info: 5: + IC(0.000 ns) + CELL(1.700 ns) = 16.700 ns; Loc. = LC2_I30; Fanout = 15; COMB LOOP Node = 'f\[0\]'" { { "Info" "ITDB_PART_OF_SCC" "f\[0\] LC2_I30 " "Info: Loc. = LC2_I30; Node \"f\[0\]\"" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { f[0] } "NODE_NAME" } } } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0} } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { f[0] } "NODE_NAME" } } { "jianzhong.vhd" "" { Text "E:/EDA/林璐雅/时钟按键1/jianzhong.vhd" 11 -1 0 } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { comb~2 f[0] } "NODE_NAME" } } { "jianzhong.vhd" "" { Text "E:/EDA/林璐雅/时钟按键1/jianzhong.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(1.400 ns) 20.200 ns Equal7~155 6 COMB LC6_I4 12 " "Info: 6: + IC(2.100 ns) + CELL(1.400 ns) = 20.200 ns; Loc. = LC6_I4; Fanout = 12; COMB Node = 'Equal7~155'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { f[0] Equal7~155 } "NODE_NAME" } } { "jianzhong.vhd" "" { Text "E:/EDA/林璐雅/时钟按键1/jianzhong.vhd" 66 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(1.400 ns) 24.700 ns \\x3:t\[0\]~34 7 COMB LC2_H27 2 " "Info: 7: + IC(3.100 ns) + CELL(1.400 ns) = 24.700 ns; Loc. = LC2_H27; Fanout = 2; COMB Node = '\\x3:t\[0\]~34'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.500 ns" { Equal7~155 \x3:t[0]~34 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(0.900 ns) 27.700 ns \\x3:t\[1\] 8 REG LC2_H3 26 " "Info: 8: + IC(2.100 ns) + CELL(0.900 ns) = 27.700 ns; Loc. = LC2_H3; Fanout = 26; REG Node = '\\x3:t\[1\]'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { \x3:t[0]~34 \x3:t[1] } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.900 ns ( 46.57 % ) " "Info: Total cell delay = 12.900 ns ( 46.57 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "14.800 ns ( 53.43 % ) " "Info: Total interconnect delay = 14.800 ns ( 53.43 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "27.700 ns" { s5 f[0]~297 comb~270 comb~2 f[0] Equal7~155 \x3:t[0]~34 \x3:t[1] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "27.700 ns" { s5 {} s5~out {} f[0]~297 {} comb~270 {} comb~2 {} f[0] {} Equal7~155 {} \x3:t[0]~34 {} \x3:t[1] {} } { 0.000ns 0.000ns 4.700ns 1.500ns 1.300ns 0.000ns 2.100ns 3.100ns 2.100ns } { 0.000ns 3.000ns 1.500ns 1.500ns 1.500ns 1.700ns 1.400ns 1.400ns 0.900ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" { } { } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.500 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns clk 1 CLK PIN_79 35 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_79; Fanout = 35; CLK Node = 'clk'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jianzhong.vhd" "" { Text "E:/EDA/林璐雅/时钟按键1/jianzhong.vhd" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 3.500 ns \\x3:t\[1\] 2 REG LC2_H3 26 " "Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC2_H3; Fanout = 26; REG Node = '\\x3:t\[1\]'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.300 ns" { clk \x3:t[1] } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 62.86 % ) " "Info: Total cell delay = 2.200 ns ( 62.86 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 37.14 % ) " "Info: Total interconnect delay = 1.300 ns ( 37.14 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { clk \x3:t[1] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { clk {} clk~out {} \x3:t[1] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "27.700 ns" { s5 f[0]~297 comb~270 comb~2 f[0] Equal7~155 \x3:t[0]~34 \x3:t[1] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "27.700 ns" { s5 {} s5~out {} f[0]~297 {} comb~270 {} comb~2 {} f[0] {} Equal7~155 {} \x3:t[0]~34 {} \x3:t[1] {} } { 0.000ns 0.000ns 4.700ns 1.500ns 1.300ns 0.000ns 2.100ns 3.100ns 2.100ns } { 0.000ns 3.000ns 1.500ns 1.500ns 1.500ns 1.700ns 1.400ns 1.400ns 0.900ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { clk \x3:t[1] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { clk {} clk~out {} \x3:t[1] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
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