jianzhong.tan.qmsg

最基本的vhdl程序

{ "Info" "ITDB_FULL_TCO_RESULT" "clk y\[7\] y\[7\]~reg0 11.200 ns register " "Info: tco from clock \"clk\" to destination pin \"y\[7\]\" through register \"y\[7\]~reg0\" is 11.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.500 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns clk 1 CLK PIN_79 35 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_79; Fanout = 35; CLK Node = 'clk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jianzhong.vhd" "" { Text "G:/d电路/EDA/林璐雅/时钟按键1/jianzhong.vhd" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 3.500 ns y\[7\]~reg0 2 REG LC1_I4 5 " "Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC1_I4; Fanout = 5; REG Node = 'y\[7\]~reg0'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.300 ns" { clk y[7]~reg0 } "NODE_NAME" } } { "jianzhong.vhd" "" { Text "G:/d电路/EDA/林璐雅/时钟按键1/jianzhong.vhd" 67 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 62.86 % ) " "Info: Total cell delay = 2.200 ns ( 62.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 37.14 % ) " "Info: Total interconnect delay = 1.300 ns ( 37.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { clk y[7]~reg0 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { clk {} clk~out {} y[7]~reg0 {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.700 ns + " "Info: + Micro clock to output delay of source is 0.700 ns" {  } { { "jianzhong.vhd" "" { Text "G:/d电路/EDA/林璐雅/时钟按键1/jianzhong.vhd" 67 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.000 ns + Longest register pin " "Info: + Longest register to pin delay is 7.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns y\[7\]~reg0 1 REG LC1_I4 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_I4; Fanout = 5; REG Node = 'y\[7\]~reg0'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { y[7]~reg0 } "NODE_NAME" } } { "jianzhong.vhd" "" { Text "G:/d电路/EDA/林璐雅/时钟按键1/jianzhong.vhd" 67 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(4.600 ns) 7.000 ns y\[7\] 2 PIN PIN_150 0 " "Info: 2: + IC(2.400 ns) + CELL(4.600 ns) = 7.000 ns; Loc. = PIN_150; Fanout = 0; PIN Node = 'y\[7\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { y[7]~reg0 y[7] } "NODE_NAME" } } { "jianzhong.vhd" "" { Text "G:/d电路/EDA/林璐雅/时钟按键1/jianzhong.vhd" 67 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.600 ns ( 65.71 % ) " "Info: Total cell delay = 4.600 ns ( 65.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.400 ns ( 34.29 % ) " "Info: Total interconnect delay = 2.400 ns ( 34.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { y[7]~reg0 y[7] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "7.000 ns" { y[7]~reg0 {} y[7] {} } { 0.000ns 2.400ns } { 0.000ns 4.600ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { clk y[7]~reg0 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { clk {} clk~out {} y[7]~reg0 {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { y[7]~reg0 y[7] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "7.000 ns" { y[7]~reg0 {} y[7] {} } { 0.000ns 2.400ns } { 0.000ns 4.600ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "lpm_counter:\\x2:i\[0\]_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[6\] clr clk -4.200 ns register " "Info: th for register \"lpm_counter:\\x2:i\[0\]_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[6\]\" (data pin = \"clr\", clock pin = \"clk\") is -4.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.500 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns clk 1 CLK PIN_79 35 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_79; Fanout = 35; CLK Node = 'clk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jianzhong.vhd" "" { Text "G:/d电路/EDA/林璐雅/时钟按键1/jianzhong.vhd" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 3.500 ns lpm_counter:\\x2:i\[0\]_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[6\] 2 REG LC2_H7 4 " "Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC2_H7; Fanout = 4; REG Node = 'lpm_counter:\\x2:i\[0\]_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[6\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.300 ns" { clk lpm_counter:\x2:i[0]_rtl_2|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/program files/altera/72/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 62.86 % ) " "Info: Total cell delay = 2.200 ns ( 62.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 37.14 % ) " "Info: Total interconnect delay = 1.300 ns ( 37.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { clk lpm_counter:\x2:i[0]_rtl_2|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { clk {} clk~out {} lpm_counter:\x2:i[0]_rtl_2|alt_counter_f10ke:wysi_counter|q[6] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.800 ns + " "Info: + Micro hold delay of destination is 0.800 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/program files/altera/72/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.500 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.700 ns) 3.700 ns clr 1 PIN PIN_53 37 " "Info: 1: + IC(0.000 ns) + CELL(3.700 ns) = 3.700 ns; Loc. = PIN_53; Fanout = 37; PIN Node = 'clr'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clr } "NODE_NAME" } } { "jianzhong.vhd" "" { Text "G:/d电路/EDA/林璐雅/时钟按键1/jianzhong.vhd" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.900 ns) + CELL(0.900 ns) 8.500 ns lpm_counter:\\x2:i\[0\]_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[6\] 2 REG LC2_H7 4 " "Info: 2: + IC(3.900 ns) + CELL(0.900 ns) = 8.500 ns; Loc. = LC2_H7; Fanout = 4; REG Node = 'lpm_counter:\\x2:i\[0\]_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[6\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.800 ns" { clr lpm_counter:\x2:i[0]_rtl_2|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/program files/altera/72/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.600 ns ( 54.12 % ) " "Info: Total cell delay = 4.600 ns ( 54.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.900 ns ( 45.88 % ) " "Info: Total interconnect delay = 3.900 ns ( 45.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.500 ns" { clr lpm_counter:\x2:i[0]_rtl_2|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "8.500 ns" { clr {} clr~out {} lpm_counter:\x2:i[0]_rtl_2|alt_counter_f10ke:wysi_counter|q[6] {} } { 0.000ns 0.000ns 3.900ns } { 0.000ns 3.700ns 0.900ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { clk lpm_counter:\x2:i[0]_rtl_2|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "3.500 ns" { clk {} clk~out {} lpm_counter:\x2:i[0]_rtl_2|alt_counter_f10ke:wysi_counter|q[6] {} } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.500 ns" { clr lpm_counter:\x2:i[0]_rtl_2|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "8.500 ns" { clr {} clr~out {} lpm_counter:\x2:i[0]_rtl_2|alt_counter_f10ke:wysi_counter|q[6] {} } { 0.000ns 0.000ns 3.900ns } { 0.000ns 3.700ns 0.900ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 11 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "120 " "Info: Allocated 120 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 24 09:22:01 2009 " "Info: Processing ended: Sun May 24 09:22:01 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}